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-rw-r--r--src/arch/arm/isa/operands.isa4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index b2c4f8420..f82e49109 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -64,8 +64,8 @@ def operands {{
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
- 'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7),
- 'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7),
+ 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
+ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),