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-rw-r--r--src/arch/arm/isa/operands.isa2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index c845acc94..e2b73e2e2 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -102,6 +102,8 @@ def operands {{
maybePCRead, maybePCWrite),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
maybePCRead, maybePCWrite),
+ 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
+ maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
maybePCRead, maybePCWrite),
'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,