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Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index f5d3e1042..244d217ce 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -76,6 +76,12 @@ def operands {{ maybePCRead, maybePCWrite), 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, maybePCRead, maybePCWrite), + 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, + maybePCRead, maybePCWrite), + 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, + maybePCRead, maybePCWrite), + 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, + maybePCRead, maybePCWrite), #General Purpose Integer Reg Operands 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), |