diff options
Diffstat (limited to 'src/arch/arm/isa/operands.isa')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 025f75755..fb3e4de35 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -46,6 +46,7 @@ def operand_types {{ 'uh' : 'uint16_t', 'sw' : 'int32_t', 'uw' : 'uint32_t', + 'sd' : 'int64_t', 'ud' : 'uint64_t', 'tud' : 'std::array<uint64_t, 2>', 'sf' : 'float', @@ -53,6 +54,10 @@ def operand_types {{ 'vc' : 'TheISA::VecRegContainer', # For operations that are implemented as a template 'x' : 'TPElem', + 'xs' : 'TPSElem', + 'xd' : 'TPDElem', + 'pc' : 'TheISA::VecPredRegContainer', + 'pb' : 'uint8_t' }}; let {{ @@ -129,6 +134,9 @@ let {{ def vectorRegElem(elem, ext = 'sf', zeroing = False): return (elem, ext, zeroing) + def vecPredReg(idx): + return ('VecPredReg', 'pc', idx, None, srtNormal) + def intReg(idx): return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, maybePCRead, maybePCWrite) @@ -522,6 +530,25 @@ def operands {{ 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True) }), + 'AA64FpDestMerge': vectorReg('dest', + { + 'AA64FpDestMergeP0': vectorRegElem('0'), + 'AA64FpDestMergeP1': vectorRegElem('1'), + 'AA64FpDestMergeP2': vectorRegElem('2'), + 'AA64FpDestMergeP3': vectorRegElem('3'), + 'AA64FpDestMergeS': vectorRegElem('0', 'sf', zeroing = True), + 'AA64FpDestMergeD': vectorRegElem('0', 'df', zeroing = True), + 'AA64FpDestMergeQ': vectorRegElem('0', 'tud', zeroing = True) + }), + + # Predicate register operands + 'GpOp': vecPredReg('gp'), + 'POp1': vecPredReg('op1'), + 'POp2': vecPredReg('op2'), + 'PDest': vecPredReg('dest'), + 'PDestMerge': vecPredReg('dest'), + 'Ffr': vecPredReg('PREDREG_FFR'), + #Abstracted control reg operands 'MiscDest': cntrlReg('dest'), 'MiscOp1': cntrlReg('op1'), |