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-rw-r--r--src/arch/arm/isa/templates/mem.isa162
1 files changed, 162 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index e44fe41db..7c93cd4ee 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -190,6 +190,77 @@ def template StoreExecute {{
}
}};
+def template StoreExExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (%(predicate_test)s)
+ {
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ uint64_t writeResult;
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, &writeResult);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ if (fault == NoFault) {
+ %(postacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
+}};
+
+def template StoreExInitiateAcc {{
+ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (%(predicate_test)s)
+ {
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ }
+
+ if (fault == NoFault) {
+ fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
+ memAccessFlags, NULL);
+ if (traceData) { traceData->setData(Mem); }
+ }
+
+ // Need to write back any potential address register update
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
+}};
+
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@@ -294,6 +365,30 @@ def template StoreCompleteAcc {{
}
}};
+def template StoreExCompleteAcc {{
+ Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ %(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (%(predicate_test)s)
+ {
+ uint64_t writeResult = pkt->req->getExtraData();
+ %(postacc_code)s;
+
+ if (fault == NoFault) {
+ %(op_wb)s;
+ }
+ }
+
+ return fault;
+ }
+}};
+
def template RfeDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -355,6 +450,27 @@ def template LoadStoreDImmDeclare {{
};
}};
+def template StoreExDImmDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst,
+ uint32_t _result, uint32_t _dest, uint32_t _dest2,
+ uint32_t _base, bool _add, int32_t _imm);
+
+ %(BasicExecDeclare)s
+
+ %(InitiateAccDeclare)s
+
+ %(CompleteAccDeclare)s
+ };
+}};
+
def template LoadStoreImmDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -375,6 +491,27 @@ def template LoadStoreImmDeclare {{
};
}};
+def template StoreExImmDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+
+ /// Constructor.
+ %(class_name)s(ExtMachInst machInst,
+ uint32_t _result, uint32_t _dest, uint32_t _base,
+ bool _add, int32_t _imm);
+
+ %(BasicExecDeclare)s
+
+ %(InitiateAccDeclare)s
+
+ %(CompleteAccDeclare)s
+ };
+}};
+
def template LoadStoreDRegDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
@@ -460,6 +597,19 @@ def template LoadStoreDImmConstructor {{
}
}};
+def template StoreExDImmConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ uint32_t _result, uint32_t _dest, uint32_t _dest2,
+ uint32_t _base, bool _add, int32_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ (IntRegIndex)_result,
+ (IntRegIndex)_dest, (IntRegIndex)_dest2,
+ (IntRegIndex)_base, _add, _imm)
+ {
+ %(constructor)s;
+ }
+}};
+
def template LoadStoreImmConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
@@ -470,6 +620,18 @@ def template LoadStoreImmConstructor {{
}
}};
+def template StoreExImmConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ uint32_t _result, uint32_t _dest, uint32_t _base,
+ bool _add, int32_t _imm)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+ (IntRegIndex)_result, (IntRegIndex)_dest,
+ (IntRegIndex)_base, _add, _imm)
+ {
+ %(constructor)s;
+ }
+}};
+
def template LoadStoreDRegConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,