summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa/templates/pred.isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/isa/templates/pred.isa')
-rw-r--r--src/arch/arm/isa/templates/pred.isa15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index b5bdbc40e..c9e7b1803 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -71,6 +71,11 @@ def template DataImmConstructor {{
_dest, _op1, _imm, _rotC)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -97,6 +102,11 @@ def template DataRegConstructor {{
_dest, _op1, _op2, _shiftAmt, _shiftType)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};
@@ -123,6 +133,11 @@ def template DataRegRegConstructor {{
_dest, _op1, _op2, _shift, _shiftType)
{
%(constructor)s;
+ if (!(condCode == COND_AL || condCode == COND_UC)) {
+ for (int x = 0; x < _numDestRegs; x++) {
+ _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
+ }
+ }
}
}};