2 files changed, 53 insertions, 1 deletions

diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 983d99af9..4f1235b03 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -71,6 +71,10 @@ def template SwapExecute {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -101,6 +105,10 @@ def template SwapInitiateAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -127,6 +135,10 @@ def template SwapCompleteAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -154,6 +166,10 @@ def template LoadExecute {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -186,6 +202,10 @@ def template StoreExecute {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -224,6 +244,10 @@ def template StoreExExecute {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -257,6 +281,10 @@ def template StoreExInitiateAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -290,6 +318,10 @@ def template StoreInitiateAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -340,6 +372,10 @@ def template LoadCompleteAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -361,6 +397,10 @@ def template StoreCompleteAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
@@ -385,6 +425,10 @@ def template StoreExCompleteAcc {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 15d34da19..c8f30ddf0 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -46,7 +46,11 @@
 //
 
 let {{
-    predicateTest = 'testPredicate(CondCodes, condCode)'
+    predicateTest = '''
+        testPredicate(CondCodes, machInst.itstateMask ?
+            (ConditionCode)(uint8_t)machInst.itstateCond :
+            condCode)
+    '''
 }};
 
 def template DataImmDeclare {{
@@ -143,6 +147,10 @@ def template PredOpExecute {{
             }
         }
 
+        if (fault == NoFault && machInst.itstateMask != 0) {
+            xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
+        }
+
         return fault;
     }
 }};