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-rw-r--r--src/arch/arm/isa/templates/pred.isa4
-rw-r--r--src/arch/arm/isa/templates/vfp.isa4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index a0f811f6d..04f253ca9 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -46,8 +46,8 @@
//
let {{
- predicateTest = 'testPredicate(OptCondCodesF, condCode)'
- condPredicateTest = 'testPredicate(CondCodesF, condCode)'
+ predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)'
+ condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)'
}};
def template DataImmDeclare {{
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 8888dc0ae..90dd751ff 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -62,6 +62,10 @@ let {{
if (op1 != (int)MISCREG_FPSCR)
return disabledFault();
'''
+ vmrsApsrEnabledCheckCode = '''
+ if (!vfpEnabled(Cpacr, Cpsr))
+ return disabledFault();
+ '''
}};
def template FpRegRegOpDeclare {{