2 files changed, 8 insertions, 38 deletions

diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index ced7a0037..29ef8d007 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -595,23 +595,11 @@ def template StoreCompleteAcc {{
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Fault fault = NoFault;
-
-        %(op_decl)s;
-        %(op_rd)s;
-
-        if (%(predicate_test)s)
-        {
-            if (fault == NoFault) {
-                %(op_wb)s;
-            }
-        }
-
-        if (fault == NoFault && machInst.itstateMask != 0) {
+        if (machInst.itstateMask != 0) {
+            warn_once("Complete acc isn't called on normal stores in O3.");
             xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
         }
-
-        return fault;
+        return NoFault;
     }
 }};
 
@@ -621,23 +609,11 @@ def template NeonStoreCompleteAcc {{
             PacketPtr pkt, %(CPU_exec_context)s *xc,
             Trace::InstRecord *traceData) const
     {
-        Fault fault = NoFault;
-
-        %(op_decl)s;
-        %(op_rd)s;
-
-        if (%(predicate_test)s)
-        {
-            if (fault == NoFault) {
-                %(op_wb)s;
-            }
-        }
-
-        if (fault == NoFault && machInst.itstateMask != 0) {
+        if (machInst.itstateMask != 0) {
+            warn_once("Complete acc isn't called on normal stores in O3.");
             xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
         }
-
-        return fault;
+        return NoFault;
     }
 }};
 
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index f8dac05f8..915dea9b0 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -387,17 +387,11 @@ def template ClrexCompleteAcc {{
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Fault fault = NoFault;
-
-        %(op_decl)s;
-        %(op_rd)s;
-
-
-        if (fault == NoFault && machInst.itstateMask != 0) {
+        if (machInst.itstateMask != 0) {
             xc->setMiscReg(MISCREG_ITSTATE, machInst.newItstate);
         }
 
-        return fault;
+        return NoFault;
     }
 }};