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-rw-r--r--src/arch/arm/isa/operands.isa13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 5ae0b8912..fe085cdac 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -82,11 +82,12 @@ def operands {{
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
- 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
- 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
- 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
- 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
- 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
- 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
+ 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', 'IsInteger', 41),
+ 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 42),
+ 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 43),
+ 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 44),
+ 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 45),
+ 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
+ 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)
}};