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-rw-r--r--src/arch/arm/isa/insts/ldr64.isa29
-rw-r--r--src/arch/arm/isa/insts/str64.isa6
-rw-r--r--src/arch/arm/isa/operands.isa2
3 files changed, 17 insertions, 20 deletions
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index eea925e66..e035e1d7e 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -198,14 +198,11 @@ let {{
'''
elif self.size == 16:
accCode = '''
- Twin64_t data = cSwap(Mem%s,
- isBigEndian64(xc->tcBase()));
-
-
- AA64FpDestP0_uw = (uint32_t)data.a;
- AA64FpDestP1_uw = (data.a >> 32);
- AA64FpDestP2_uw = (uint32_t)data.b;
- AA64FpDestP3_uw = (data.b >> 32);
+ auto data = cSwap(Mem%s, isBigEndian64(xc->tcBase()));
+ AA64FpDestP0_uw = (uint32_t)data[0];
+ AA64FpDestP1_uw = (data[0] >> 32);
+ AA64FpDestP2_uw = (uint32_t)data[1];
+ AA64FpDestP3_uw = (data[1] >> 32);
'''
elif self.flavor == "widen" or self.size == 8:
accCode = "XDest = cSwap(Mem%s, isBigEndian64(xc->tcBase()));"
@@ -242,12 +239,12 @@ let {{
'''
elif self.size == 8:
accCode = '''
- AA64FpDestP0_uw = (uint32_t)Mem_tud.a;
- AA64FpDestP1_uw = (uint32_t)(Mem_tud.a >> 32);
+ AA64FpDestP0_uw = (uint32_t)Mem_tud[0];
+ AA64FpDestP1_uw = (uint32_t)(Mem_tud[0] >> 32);
AA64FpDestP2_uw = 0;
AA64FpDestP3_uw = 0;
- AA64FpDest2P0_uw = (uint32_t)Mem_tud.b;
- AA64FpDest2P1_uw = (uint32_t)(Mem_tud.b >> 32);
+ AA64FpDest2P0_uw = (uint32_t)Mem_tud[1];
+ AA64FpDest2P1_uw = (uint32_t)(Mem_tud[1] >> 32);
AA64FpDest2P2_uw = 0;
AA64FpDest2P3_uw = 0;
'''
@@ -262,8 +259,8 @@ let {{
'''
elif self.size == 8:
accCode = '''
- XDest = Mem_tud.a;
- XDest2 = Mem_tud.b;
+ XDest = Mem_tud[0];
+ XDest2 = Mem_tud[1];
'''
else:
if self.size == 4:
@@ -275,8 +272,8 @@ let {{
'''
elif self.size == 8:
accCode = '''
- XDest = Mem_tud.a;
- XDest2 = Mem_tud.b;
+ XDest = Mem_tud[0];
+ XDest2 = Mem_tud[1];
'''
self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index 0b153c1ec..324d1fc69 100644
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -226,9 +226,9 @@ let {{
accCode = '''
// This temporary needs to be here so that the parser
// will correctly identify this instruction as a store.
- Twin64_t temp;
- temp.a = XDest_ud;
- temp.b = XDest2_ud;
+ std::array<uint64_t, 2> temp;
+ temp[0] = XDest_ud;
+ temp[1] = XDest2_ud;
Mem_tud = temp;
'''
self.codeBlobs["memacc_code"] = accCode
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 2e2955a80..babf0accf 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -47,7 +47,7 @@ def operand_types {{
'sw' : 'int32_t',
'uw' : 'uint32_t',
'ud' : 'uint64_t',
- 'tud' : 'Twin64_t',
+ 'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
'vc' : 'TheISA::VecRegContainer',