diff options
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/m5ops.isa | 2 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/m5ops.isa | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa index 2f5fe2c3a..f532d828b 100644 --- a/src/arch/arm/isa/formats/m5ops.isa +++ b/src/arch/arm/isa/formats/m5ops.isa @@ -72,6 +72,8 @@ def format M5ops() {{ case 0x53: return new M5addsymbol(machInst); #endif case 0x54: return new M5panic(machInst); + case 0x5a: return new M5workbegin(machInst); + case 0x5b: return new M5workend(machInst); } } ''' diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index b48e72b8a..9bd1f4f01 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -313,4 +313,30 @@ let {{ decoder_output += BasicConstructor.subst(m5panicIop) exec_output += PredOpExecute.subst(m5panicIop) + m5workbeginCode = '''PseudoInst::workbegin( + xc->tcBase(), + join32to64(R1, R0), + join32to64(R3, R2) + );''' + m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", + { "code": m5workbeginCode, + "predicate_test": predicateTest }, + ["IsNonSpeculative"]) + header_output += BasicDeclare.subst(m5workbeginIop) + decoder_output += BasicConstructor.subst(m5workbeginIop) + exec_output += PredOpExecute.subst(m5workbeginIop) + + m5workendCode = '''PseudoInst::workend( + xc->tcBase(), + join32to64(R1, R0), + join32to64(R3, R2) + );''' + m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", + { "code": m5workendCode, + "predicate_test": predicateTest }, + ["IsNonSpeculative"]) + header_output += BasicDeclare.subst(m5workendIop) + decoder_output += BasicConstructor.subst(m5workendIop) + exec_output += PredOpExecute.subst(m5workendIop) + }}; |