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-rw-r--r--src/arch/arm/isa/formats/fp.isa18
-rw-r--r--src/arch/arm/isa/insts/fp.isa4
-rw-r--r--src/arch/arm/isa/insts/m5ops.isa19
-rw-r--r--src/arch/arm/isa/insts/macromem.isa7
-rw-r--r--src/arch/arm/isa/insts/neon.isa16
-rw-r--r--src/arch/arm/isa/templates/mem.isa4
6 files changed, 28 insertions, 40 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 812338c30..0cb27d7f1 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -561,20 +561,22 @@ let {{
}
}
case 0xa:
+ if (q)
+ return new Unknown(machInst);
if (b) {
- return decodeNeonUSThreeReg<VpminD, VpminQ>(
- q, u, size, machInst, vd, vn, vm);
+ return decodeNeonUSThreeUSReg<VpminD>(
+ u, size, machInst, vd, vn, vm);
} else {
- return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>(
- q, u, size, machInst, vd, vn, vm);
+ return decodeNeonUSThreeUSReg<VpmaxD>(
+ u, size, machInst, vd, vn, vm);
}
case 0xb:
if (b) {
- if (u) {
+ if (u || q) {
return new Unknown(machInst);
} else {
- return decodeNeonUThreeReg<NVpaddD, NVpaddQ>(
- q, size, machInst, vd, vn, vm);
+ return decodeNeonUThreeUSReg<NVpaddD>(
+ size, machInst, vd, vn, vm);
}
} else {
if (u) {
@@ -1542,7 +1544,7 @@ let {{
else
return new NVswpD<uint64_t>(machInst, vd, vm);
case 0x1:
- return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>(
+ return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>(
q, size, machInst, vd, vm);
case 0x2:
return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>(
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index f82858bbd..b701995f4 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -447,7 +447,7 @@ let {{
exec_output = ""
singleSimpleCode = vfpEnabledCheckCode + '''
- FPSCR fpscr = (FPSCR) FpscrExc;
+ FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
FpDest = %(op)s;
'''
singleCode = singleSimpleCode + '''
@@ -457,7 +457,7 @@ let {{
"%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
doubleCode = vfpEnabledCheckCode + '''
- FPSCR fpscr = (FPSCR) FpscrExc;
+ FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
double dest = %(op)s;
FpDestP0_uw = dblLow(dest);
FpDestP1_uw = dblHi(dest);
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index e891a0a91..3b837cba9 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -54,9 +54,7 @@ let {{
armCode = '''
-#if FULL_SYSTEM
PseudoInst::arm(xc->tcBase());
-#endif
'''
armIop = InstObjParams("arm", "Arm", "PredOp",
{ "code": armCode,
@@ -67,9 +65,7 @@ let {{
exec_output += PredOpExecute.subst(armIop)
quiesceCode = '''
-#if FULL_SYSTEM
PseudoInst::quiesce(xc->tcBase());
-#endif
'''
quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
{ "code": quiesceCode,
@@ -80,9 +76,7 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceIop)
quiesceNsCode = '''
-#if FULL_SYSTEM
PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
-#endif
'''
quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
@@ -94,9 +88,7 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
quiesceCyclesCode = '''
-#if FULL_SYSTEM
PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
-#endif
'''
quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
@@ -108,11 +100,9 @@ let {{
exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
quiesceTimeCode = '''
-#if FULL_SYSTEM
uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
R0 = bits(qt_val, 31, 0);
R1 = bits(qt_val, 63, 32);
-#endif
'''
quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
@@ -188,9 +178,7 @@ let {{
exec_output += PredOpExecute.subst(m5exitIop)
loadsymbolCode = '''
-#if FULL_SYSTEM
PseudoInst::loadsymbol(xc->tcBase());
-#endif
'''
loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
@@ -204,6 +192,9 @@ let {{
initparamCode = '''
#if FULL_SYSTEM
Rt = PseudoInst::initParam(xc->tcBase());
+#else
+ PseudoInst::panicFsOnlyPseudoInst("initparam");
+ Rt = 0;
#endif
'''
@@ -260,11 +251,9 @@ let {{
exec_output += PredOpExecute.subst(m5checkpointIop)
m5readfileCode = '''
-#if FULL_SYSTEM
int n = 4;
uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
-#endif
'''
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
{ "code": m5readfileCode,
@@ -291,9 +280,7 @@ let {{
exec_output += PredOpExecute.subst(m5switchcpuIop)
m5addsymbolCode = '''
-#if FULL_SYSTEM
PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
-#endif
'''
m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
{ "code": m5addsymbolCode,
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 815d4c258..db36a3fff 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -563,15 +563,16 @@ let {{
let {{
exec_output = ''
- for type in ('uint8_t', 'uint16_t', 'uint32_t'):
+ for typeSize in (8, 16, 32):
for sRegs in 1, 2:
- for dRegs in range(sRegs, 5):
+ for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)):
for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
"MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
"MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
Name = format % { "sRegs" : sRegs * 2,
"dRegs" : dRegs * 2 }
- substDict = { "class_name" : Name, "targs" : type }
+ substDict = { "class_name" : Name,
+ "targs" : "uint%d_t" % typeSize }
exec_output += MicroNeonExecDeclare.subst(substDict)
}};
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index fdb6237c0..dd0d49a5c 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1619,10 +1619,8 @@ let {{
threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode)
threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode)
- threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes,
+ threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes,
2, vaddCode, pairwise=True)
- threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes,
- 4, vaddCode, pairwise=True)
vaddlwCode = '''
destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
'''
@@ -2113,11 +2111,9 @@ let {{
'''
threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode)
- threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True)
- threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True)
+ threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True)
- threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True)
- threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True)
+ threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True)
vqdmulhCode = '''
FPSCR fpscr = (FPSCR) FpscrQc;
@@ -3140,8 +3136,10 @@ let {{
destReg.elements[i + 1] = mid;
}
'''
- twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode)
- twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode)
+ twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp",
+ smallUnsignedTypes, 2, vtrnCode)
+ twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp",
+ smallUnsignedTypes, 4, vtrnCode)
vuzpCode = '''
Element mid[eCount];
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index a00114409..a4a740f89 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{
(IntRegIndex)_index)
{
%(constructor)s;
- bool conditional = false;
+ bool conditional M5_VAR_USED = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
@@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
- bool conditional = false;
+ bool conditional M5_VAR_USED = false;
if (!(condCode == COND_AL || condCode == COND_UC)) {
conditional = true;
for (int x = 0; x < _numDestRegs; x++) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 15:04:51 +0000