summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/formats/fp.isa8
-rw-r--r--src/arch/arm/isa/formats/pred.isa36
-rw-r--r--src/arch/arm/isa/insts/data.isa42
-rw-r--r--src/arch/arm/isa/insts/fp.isa16
-rw-r--r--src/arch/arm/isa/insts/ldr.isa8
-rw-r--r--src/arch/arm/isa/insts/macromem.isa40
-rw-r--r--src/arch/arm/isa/insts/mem.isa31
-rw-r--r--src/arch/arm/isa/insts/misc.isa48
-rw-r--r--src/arch/arm/isa/insts/mult.isa2
-rw-r--r--src/arch/arm/isa/insts/str.isa2
-rw-r--r--src/arch/arm/isa/operands.isa21
-rw-r--r--src/arch/arm/isa/templates/pred.isa4
-rw-r--r--src/arch/arm/isa/templates/vfp.isa4
13 files changed, 171 insertions, 91 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 5ec65c01b..812338c30 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -2068,14 +2068,8 @@ let {{
return new Unknown(machInst);
}
if (rt == 0xf) {
- CPSR cpsrMask = 0;
- cpsrMask.n = 1;
- cpsrMask.z = 1;
- cpsrMask.c = 1;
- cpsrMask.v = 1;
if (specReg == MISCREG_FPSCR) {
- return new VmrsApsrFpscr(machInst, INTREG_CONDCODES_F,
- (IntRegIndex)specReg, (uint32_t)cpsrMask);
+ return new VmrsApsrFpscr(machInst);
} else {
return new Unknown(machInst);
}
diff --git a/src/arch/arm/isa/formats/pred.isa b/src/arch/arm/isa/formats/pred.isa
index 89fcd9ca9..bd6ccddd1 100644
--- a/src/arch/arm/isa/formats/pred.isa
+++ b/src/arch/arm/isa/formats/pred.isa
@@ -53,7 +53,9 @@ let {{
_iv = %(ivValue)s & 1;
_ic = %(icValue)s & 1;
- CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
+ CondCodesNZ = (_in << 1) | (_iz);
+ CondCodesC = _ic;
+ CondCodesV = _iv;
DPRINTF(Arm, "in = %%d\\n", _in);
DPRINTF(Arm, "iz = %%d\\n", _iz);
@@ -70,11 +72,11 @@ let {{
canOverflow = 'false'
if flagtype == "none":
- icReg = icImm = 'CondCodesF<29:>'
- iv = 'CondCodesF<28:>'
+ icReg = icImm = 'CondCodesC'
+ iv = 'CondCodesV'
elif flagtype == "llbit":
- icReg = icImm = 'CondCodesF<29:>'
- iv = 'CondCodesF<28:>'
+ icReg = icImm = 'CondCodesC'
+ iv = 'CondCodesV'
negBit = 63
elif flagtype == "overflow":
canOverflow = "true"
@@ -89,9 +91,9 @@ let {{
icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
iv = 'findOverflow(32, resTemp, op2, ~Rn)'
else:
- icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesF<29:>)'
- icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesF<29:>)'
- iv = 'CondCodesF<28:>'
+ icReg = 'shift_carry_rs(Rm, Rs<7:0>, shift, CondCodesC)'
+ icImm = 'shift_carry_imm(Rm, shift_size, shift, CondCodesC)'
+ iv = 'CondCodesV'
return (calcCcCode % {"icValue" : icReg,
"ivValue" : iv,
"negBit" : negBit,
@@ -106,11 +108,11 @@ let {{
negBit = 31
canOverflow = 'false'
if flagtype == "none":
- icValue = 'CondCodesF<29:>'
- ivValue = 'CondCodesF<28:>'
+ icValue = 'CondCodesC'
+ ivValue = 'CondCodesV'
elif flagtype == "llbit":
- icValue = 'CondCodesF<29:>'
- ivValue = 'CondCodesF<28:>'
+ icValue = 'CondCodesC'
+ ivValue = 'CondCodesV'
negBit = 63
elif flagtype == "overflow":
icVaule = ivValue = '0'
@@ -126,20 +128,20 @@ let {{
ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
elif flagtype == "modImm":
icValue = 'rotated_carry'
- ivValue = 'CondCodesF<28:>'
+ ivValue = 'CondCodesV'
else:
- icValue = '(rotate ? rotated_carry:CondCodesF<29:>)'
- ivValue = 'CondCodesF<28:>'
+ icValue = '(rotate ? rotated_carry:CondCodesC)'
+ ivValue = 'CondCodesV'
return calcCcCode % vars()
}};
def format DataOp(code, flagtype = logic) {{
(regCcCode, immCcCode) = getCcCode(flagtype)
regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs<7:0>,
- shift, CondCodesF<29:>);
+ shift, CondCodesC);
op2 = op2;''' + code
immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
- shift, CondCodesF<29:>);
+ shift, CondCodesC);
op2 = op2;''' + code
regIop = InstObjParams(name, Name, 'PredIntOp',
{"code": regCode,
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 1a239f48b..94693c8ef 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -44,7 +44,7 @@ let {{
exec_output = ""
calcGECode = '''
- CondCodesGE = insertBits(0, 19, 16, resTemp);
+ CondCodesGE = resTemp;
'''
calcQCode = '''
@@ -58,15 +58,17 @@ let {{
_iv = %(ivValue)s & 1;
_ic = %(icValue)s & 1;
- CondCodesF = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28;
+ CondCodesNZ = (_in << 1) | _iz;
+ CondCodesC = _ic;
+ CondCodesV = _iv;
DPRINTF(Arm, "(in, iz, ic, iv) = (%%d, %%d, %%d, %%d)\\n",
_in, _iz, _ic, _iv);
'''
# Dict of code to set the carry flag. (imm, reg, reg-reg)
- oldC = 'CondCodesF<29:>'
- oldV = 'CondCodesF<28:>'
+ oldC = 'CondCodesC'
+ oldV = 'CondCodesV'
carryCode = {
"none": (oldC, oldC, oldC),
"llbit": (oldC, oldC, oldC),
@@ -101,8 +103,8 @@ let {{
secondOpRe = re.compile("secondOp")
immOp2 = "imm"
- regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesF<29:>)"
- regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesF<29:>)"
+ regOp2 = "shift_rm_imm(Op2, shiftAmt, shiftType, CondCodesC)"
+ regRegOp2 = "shift_rm_rs(Op2, Shift<7:0>, shiftType, CondCodesC)"
def buildImmDataInst(mnem, code, flagType = "logic", suffix = "Imm", \
buildCc = True, buildNonCc = True, instFlags = []):
@@ -238,16 +240,24 @@ let {{
if subsPcLr:
code += '''
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE,
- Spsr, 0xF, true, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
- NextThumb = ((CPSR)newCpsr).t;
- NextJazelle = ((CPSR)newCpsr).j;
- NextItState = ((((CPSR)newCpsr).it2 << 2) & 0xFC)
- | (((CPSR)newCpsr).it1 & 0x3);
+ CPSR old_cpsr = Cpsr;
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
+
+ NextThumb = (new_cpsr).t;
+ NextJazelle = (new_cpsr).j;
+ NextItState = (((new_cpsr).it2 << 2) & 0xFC)
+ | ((new_cpsr).it1 & 0x3);
SevMailbox = 1;
'''
buildImmDataInst(mnem + 's', code, flagType,
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 53d0b3413..73b3aa50e 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -235,16 +235,18 @@ let {{
decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop);
exec_output += PredOpExecute.subst(vmrsFpscrIop);
- vmrsApsrFpscrCode = vmrsEnabledCheckCode + '''
- Dest = FpCondCodes & FpCondCodesMask;
+ vmrsApsrFpscrCode = vmrsApsrEnabledCheckCode + '''
+ FPSCR fpscr = FpCondCodes;
+ CondCodesNZ = (fpscr.n << 1) | fpscr.z;
+ CondCodesC = fpscr.c;
+ CondCodesV = fpscr.v;
'''
- vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "FpRegRegImmOp",
+ vmrsApsrFpscrIop = InstObjParams("vmrs", "VmrsApsrFpscr", "PredOp",
{ "code": vmrsApsrFpscrCode,
"predicate_test": predicateTest,
- "op_class": "SimdFloatMiscOp" },
- ["IsSerializeBefore"])
- header_output += FpRegRegImmOpDeclare.subst(vmrsApsrFpscrIop);
- decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrFpscrIop);
+ "op_class": "SimdFloatMiscOp" })
+ header_output += BasicDeclare.subst(vmrsApsrFpscrIop);
+ decoder_output += BasicConstructor.subst(vmrsApsrFpscrIop);
exec_output += PredOpExecute.subst(vmrsApsrFpscrIop);
vmovImmSCode = vfpEnabledCheckCode + '''
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 9211983d4..a346c495a 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -106,7 +106,11 @@ let {{
wbDiff = 8
accCode = '''
CPSR cpsr = Cpsr;
- URc = cpsr | CondCodesF | CondCodesGE;
+ cpsr.nz = CondCodesNZ;
+ cpsr.c = CondCodesC;
+ cpsr.v = CondCodesV;
+ cpsr.ge = CondCodesGE;
+ URc = cpsr;
URa = cSwap<uint32_t>(Mem.ud, cpsr.e);
URb = cSwap<uint32_t>(Mem.ud >> 32, cpsr.e);
'''
@@ -137,7 +141,7 @@ let {{
def __init__(self, *args, **kargs):
super(LoadRegInst, self).__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
- " shiftType, CondCodesF<29:>)"
+ " shiftType, CondCodesC)"
if self.add:
self.wbDecl = '''
MicroAddUop(machInst, base, base, wbIndexReg, shiftAmt, shiftType);
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 8523b840c..31545d3a4 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -87,15 +87,21 @@ let {{
['IsMicroop'])
microRetUopCode = '''
- CPSR cpsr = Cpsr;
+ CPSR old_cpsr = Cpsr;
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(cpsr | CondCodesF | CondCodesGE,
- Spsr, 0xF, true, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
- IWNPC = cSwap(%s, cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, Spsr, 0xF, true, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
+ IWNPC = cSwap(%s, old_cpsr.e) | ((Spsr & 0x20) ? 1 : 0);
NextItState = ((((CPSR)Spsr).it2 << 2) & 0xFC)
| (((CPSR)Spsr).it1 & 0x3);
SevMailbox = 1;
@@ -587,7 +593,7 @@ let {{
{'code':
'''URa = URb + shift_rm_imm(URc, shiftAmt,
shiftType,
- CondCodesF<29:>);
+ CondCodesC);
''',
'predicate_test': predicateTest},
['IsMicroop'])
@@ -603,7 +609,7 @@ let {{
{'code':
'''URa = URb - shift_rm_imm(URc, shiftAmt,
shiftType,
- CondCodesF<29:>);
+ CondCodesC);
''',
'predicate_test': predicateTest},
['IsMicroop'])
@@ -625,16 +631,18 @@ let {{
CPSR cpsrOrCondCodes = URc;
SCTLR sctlr = Sctlr;
pNPC = URa;
- uint32_t newCpsr =
+ CPSR new_cpsr =
cpsrWriteByInstr(cpsrOrCondCodes, URb,
0xF, true, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- NextThumb = ((CPSR)newCpsr).t;
- NextJazelle = ((CPSR)newCpsr).j;
+ Cpsr = ~CondCodesMask & new_cpsr;
+ NextThumb = new_cpsr.t;
+ NextJazelle = new_cpsr.j;
NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
| (((CPSR)URb).it1 & 0x3);
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
'''
microUopSetPCCPSRIop = InstObjParams('uopSet_uop', 'MicroUopSetPCCPSR',
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 0ebd34ad4..cad0b1589 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -119,10 +119,35 @@ let {{
return (header_output, decoder_output, exec_output)
def pickPredicate(blobs):
+ opt_nz = True
+ opt_c = True
+ opt_v = True
for val in blobs.values():
- if re.search('(?<!Opt)CondCodesF', val):
- return condPredicateTest
- return predicateTest
+ if re.search('(?<!Opt)CondCodesNZ', val):
+ opt_nz = False
+ if re.search('(?<!Opt)CondCodesC', val):
+ opt_c = False
+ if re.search('(?<!Opt)CondCodesV', val):
+ opt_v = False
+
+ # Build up the predicate piece by piece depending on which
+ # flags the instruction needs
+ predicate = 'testPredicate('
+ if opt_nz:
+ predicate += 'OptCondCodesNZ, '
+ else:
+ predicate += 'CondCodesNZ, '
+ if opt_c:
+ predicate += 'OptCondCodesC, '
+ else:
+ predicate += 'CondCodesC, '
+ if opt_v:
+ predicate += 'OptCondCodesV, '
+ else:
+ predicate += 'CondCodesV, '
+ predicate += 'condCode)'
+
+ return predicate
def memClassName(base, post, add, writeback, \
size=4, sign=False, user=False):
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index c22384212..c270db499 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -61,7 +61,12 @@ let {{
header_output = decoder_output = exec_output = ""
mrsCpsrCode = '''
- Dest = (Cpsr | CondCodesF | CondCodesGE) & 0xF8FF03DF
+ CPSR cpsr = Cpsr;
+ cpsr.nz = CondCodesNZ;
+ cpsr.c = CondCodesC;
+ cpsr.v = CondCodesV;
+ cpsr.ge = CondCodesGE;
+ Dest = cpsr & 0xF8FF03DF
'''
mrsCpsrIop = InstObjParams("mrs", "MrsCpsr", "MrsOp",
@@ -83,12 +88,19 @@ let {{
msrCpsrRegCode = '''
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, Op1,
- byteMask, false, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
+ CPSR old_cpsr = Cpsr;
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, Op1, byteMask, false, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
'''
msrCpsrRegIop = InstObjParams("msr", "MsrCpsrReg", "MsrRegOp",
{ "code": msrCpsrRegCode,
@@ -109,12 +121,18 @@ let {{
msrCpsrImmCode = '''
SCTLR sctlr = Sctlr;
- uint32_t newCpsr =
- cpsrWriteByInstr(Cpsr | CondCodesF | CondCodesGE, imm,
- byteMask, false, sctlr.nmfi);
- Cpsr = ~CondCodesMask & newCpsr;
- CondCodesF = CondCodesMaskF & newCpsr;
- CondCodesGE = CondCodesMaskGE & newCpsr;
+ CPSR old_cpsr = Cpsr;
+ old_cpsr.nz = CondCodesNZ;
+ old_cpsr.c = CondCodesC;
+ old_cpsr.v = CondCodesV;
+ old_cpsr.ge = CondCodesGE;
+ CPSR new_cpsr =
+ cpsrWriteByInstr(old_cpsr, imm, byteMask, false, sctlr.nmfi);
+ Cpsr = ~CondCodesMask & new_cpsr;
+ CondCodesNZ = new_cpsr.nz;
+ CondCodesC = new_cpsr.c;
+ CondCodesV = new_cpsr.v;
+ CondCodesGE = new_cpsr.ge;
'''
msrCpsrImmIop = InstObjParams("msr", "MsrCpsrImm", "MsrImmOp",
{ "code": msrCpsrImmCode,
@@ -415,14 +433,14 @@ let {{
int low = i * 8;
int high = low + 7;
replaceBits(resTemp, high, low,
- bits(CondCodesGE, 16 + i) ?
+ bits(CondCodesGE, i) ?
bits(Op1, high, low) : bits(Op2, high, low));
}
Dest = resTemp;
'''
selIop = InstObjParams("sel", "Sel", "RegRegRegOp",
{ "code": selCode,
- "predicate_test": condPredicateTest }, [])
+ "predicate_test": predicateTest }, [])
header_output += RegRegRegOpDeclare.subst(selIop)
decoder_output += RegRegRegOpConstructor.subst(selIop)
exec_output += PredOpExecute.subst(selIop)
diff --git a/src/arch/arm/isa/insts/mult.isa b/src/arch/arm/isa/insts/mult.isa
index 31febe747..f4f8b867e 100644
--- a/src/arch/arm/isa/insts/mult.isa
+++ b/src/arch/arm/isa/insts/mult.isa
@@ -52,7 +52,7 @@ let {{
_in = (resTemp >> %(negBit)d) & 1;
_iz = ((%(zType)s)resTemp == 0);
- CondCodesF = _in << 31 | _iz << 30 | (CondCodesF & 0x3FFFFFFF);
+ CondCodesNZ = (_in << 1) | _iz;
DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
'''
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 312bcac16..95ba4ad39 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -152,7 +152,7 @@ let {{
def __init__(self, *args, **kargs):
super(StoreRegInst, self).__init__(*args, **kargs)
self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
- " shiftType, CondCodesF<29:>)"
+ " shiftType, CondCodesC)"
if self.add:
self.wbDecl = '''
MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index ead058b4c..058cc94f3 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -156,11 +156,24 @@ def operands {{
'R3': intRegNPC('3'),
#Pseudo integer condition code registers
- 'CondCodesF': intRegCC('INTREG_CONDCODES_F'),
+ 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
+ 'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
+ 'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
- 'OptCondCodesF': intRegCC(
- '''(condCode == COND_AL || condCode == COND_UC) ?
- INTREG_ZERO : INTREG_CONDCODES_F'''),
+ 'OptCondCodesNZ': intRegCC(
+ '''(condCode == COND_AL || condCode == COND_UC ||
+ condCode == COND_CC || condCode == COND_CS ||
+ condCode == COND_VS || condCode == COND_VC) ?
+ INTREG_ZERO : INTREG_CONDCODES_NZ'''),
+ 'OptCondCodesC': intRegCC(
+ '''(condCode == COND_HI || condCode == COND_LS ||
+ condCode == COND_CS || condCode == COND_CC) ?
+ INTREG_CONDCODES_C : INTREG_ZERO'''),
+ 'OptCondCodesV': intRegCC(
+ '''(condCode == COND_VS || condCode == COND_VC ||
+ condCode == COND_GE || condCode == COND_LT ||
+ condCode == COND_GT || condCode == COND_LE) ?
+ INTREG_CONDCODES_V : INTREG_ZERO'''),
'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
#Abstracted floating point reg operands
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index a0f811f6d..04f253ca9 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -46,8 +46,8 @@
//
let {{
- predicateTest = 'testPredicate(OptCondCodesF, condCode)'
- condPredicateTest = 'testPredicate(CondCodesF, condCode)'
+ predicateTest = 'testPredicate(OptCondCodesNZ, OptCondCodesC, OptCondCodesV, condCode)'
+ condPredicateTest = 'testPredicate(CondCodesNZ, CondCodesC, CondCodesV, condCode)'
}};
def template DataImmDeclare {{
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 8888dc0ae..90dd751ff 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -62,6 +62,10 @@ let {{
if (op1 != (int)MISCREG_FPSCR)
return disabledFault();
'''
+ vmrsApsrEnabledCheckCode = '''
+ if (!vfpEnabled(Cpacr, Cpsr))
+ return disabledFault();
+ '''
}};
def template FpRegRegOpDeclare {{
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 02:10:40 +0000