diff options
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/aarch64.isa | 9 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 8 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 2 |
3 files changed, 13 insertions, 6 deletions
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa index 04a8ba527..b5a4dfa21 100644 --- a/src/arch/arm/isa/formats/aarch64.isa +++ b/src/arch/arm/isa/formats/aarch64.isa @@ -366,9 +366,12 @@ namespace Aarch64 if (miscReg == MISCREG_DC_ZVA_Xt && !read) return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss); - if (read) - return new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); - else + if (read) { + StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss); + if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) + si->setFlag(StaticInst::IsUnverifiable); + return si; + } else return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss); } else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) { std::string full_mnem = csprintf("%s %s", diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 925ed55cd..f81b96f2f 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -273,8 +273,12 @@ let {{ if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1); - if (isRead) - return new Mrrc15(machInst, miscReg, rt2, rt, iss); + if (isRead) { + StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss); + if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE]) + si->setFlag(StaticInst::IsUnverifiable); + return si; + } return new Mcrr15(machInst, rt2, rt, miscReg, iss); } else { return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst, diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 5403ddc8d..6ecaa78de 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -219,7 +219,7 @@ let {{ msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", { "code": msrBankedRegCode, "predicate_test": predicateTest }, - ["IsSerializeAfter"]) + ["IsSerializeAfter", "IsNonSpeculative"]) header_output += MsrBankedRegDeclare.subst(msrBankedRegIop) decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop) exec_output += PredOpExecute.subst(msrBankedRegIop) |