diff options
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 19 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 14 |
2 files changed, 33 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index be0e63900..2801ebedf 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -137,6 +137,8 @@ let {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); + + // Write only. case MISCREG_TLBIALLIS: case MISCREG_TLBIMVAIS: case MISCREG_TLBIASIDIS: @@ -157,6 +159,23 @@ let {{ return new Mcr15(machInst, (IntRegIndex)miscReg, rt); } + // Read only in user mode. + case MISCREG_TPIDRURO: + if (isRead) { + return new Mrc15User(machInst, rt, (IntRegIndex)miscReg); + } else { + return new Mcr15(machInst, (IntRegIndex)miscReg, rt); + } + + // Read/write in user mode. + case MISCREG_TPIDRURW: + if (isRead) { + return new Mrc15User(machInst, rt, (IntRegIndex)miscReg); + } else { + return new Mcr15User(machInst, (IntRegIndex)miscReg, rt); + } + + // Read/write, priveleged only. default: if (isRead) { return new Mrc15(machInst, rt, (IntRegIndex)miscReg); diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 7f9a5c171..6b81853f1 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -614,6 +614,20 @@ let {{ decoder_output += RegRegOpConstructor.subst(mcr15Iop) exec_output += PredOpExecute.subst(mcr15Iop) + mrc15UserIop = InstObjParams("mrc", "Mrc15User", "RegRegOp", + { "code": "Dest = MiscOp1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc15UserIop) + decoder_output += RegRegOpConstructor.subst(mrc15UserIop) + exec_output += PredOpExecute.subst(mrc15UserIop) + + mcr15UserIop = InstObjParams("mcr", "Mcr15User", "RegRegOp", + { "code": "MiscDest = Op1", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mcr15UserIop) + decoder_output += RegRegOpConstructor.subst(mcr15UserIop) + exec_output += PredOpExecute.subst(mcr15UserIop) + enterxCode = ''' FNPC = NPC | (1ULL << PcJBitShift) | (1ULL << PcTBitShift); ''' |