diff options
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 12 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/ldr.isa | 26 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/mem.isa | 26 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/str.isa | 19 | ||||
-rw-r--r-- | src/arch/arm/isa/operands.isa | 6 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 70 |
6 files changed, 124 insertions, 35 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index 311ae5b66..1c69a5e00 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -150,6 +150,10 @@ def format AddrMode3() {{ addStr = "true" else: addStr = "false" + if d: + dests = "RT & ~1, RT | 1" + else: + dests = "RT" if i: if load: if d: @@ -165,8 +169,8 @@ def format AddrMode3() {{ className = storeImmClassName(post, add, writeback, \ size=size, sign=sign, \ user=user) - decode += ("%s(machInst, RT, RN, %s, imm);\n" % \ - (className, addStr)) + decode += ("%s(machInst, %s, RN, %s, imm);\n" % \ + (className, dests, addStr)) else: if load: if d: @@ -182,8 +186,8 @@ def format AddrMode3() {{ className = storeRegClassName(post, add, writeback, \ size=size, sign=sign, \ user=user) - decode += ("%s(machInst, RT, RN, %s, 0, LSL, RM);\n" % \ - (className, addStr)) + decode += ("%s(machInst, %s, RN, %s, 0, LSL, RM);\n" % \ + (className, dests, addStr)) return decode def decodePuiw(load, d, size=4, sign=False): diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa index da20cab0b..6b8c925b6 100644 --- a/src/arch/arm/isa/insts/ldr.isa +++ b/src/arch/arm/isa/insts/ldr.isa @@ -59,14 +59,15 @@ let {{ def loadDoubleRegClassName(post, add, writeback): return memClassName("LOAD_REGD", post, add, writeback, 4, False, False) - def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base): + def emitLoad(name, Name, imm, eaCode, accCode, \ + memFlags, instFlags, base, double=False): global header_output, decoder_output, exec_output (newHeader, newDecoder, newExec) = loadStoreBase(name, Name, imm, eaCode, accCode, - memFlags, instFlags, + memFlags, instFlags, double, base, execTemplateBase = 'Load') header_output += newHeader @@ -143,7 +144,8 @@ let {{ accCode += "Base = Base %s;\n" % offset base = buildMemBase("MemoryReg", post, writeback) - emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base) + emitLoad(name, Name, False, eaCode, accCode, \ + memFlags, [], base) def buildDoubleImmLoad(mnem, post, add, writeback, ldrex=False): name = mnem @@ -161,8 +163,8 @@ let {{ eaCode += ";" accCode = ''' - Rdo = bits(Mem.ud, 31, 0); - Rde = bits(Mem.ud, 63, 32); + Dest = bits(Mem.ud, 31, 0); + Dest2 = bits(Mem.ud, 63, 32); ''' if ldrex: memFlags = ["Request::LLSC"] @@ -171,9 +173,10 @@ let {{ memFlags = [] if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryImm", post, writeback) + base = buildMemBase("MemoryDImm", post, writeback) - emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base) + emitLoad(name, Name, True, eaCode, accCode, \ + memFlags, [], base, double=True) def buildDoubleRegLoad(mnem, post, add, writeback): name = mnem @@ -192,14 +195,15 @@ let {{ eaCode += ";" accCode = ''' - Rdo = bits(Mem.ud, 31, 0); - Rde = bits(Mem.ud, 63, 32); + Dest = bits(Mem.ud, 31, 0); + Dest2 = bits(Mem.ud, 63, 32); ''' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryReg", post, writeback) + base = buildMemBase("MemoryDReg", post, writeback) - emitLoad(name, Name, False, eaCode, accCode, [], [], base) + emitLoad(name, Name, False, eaCode, accCode, + [], [], base, double=True) def buildLoads(mnem, size=4, sign=False, user=False): buildImmLoad(mnem, True, True, True, size, sign, user) diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa index 21687b225..dc447cf8b 100644 --- a/src/arch/arm/isa/insts/mem.isa +++ b/src/arch/arm/isa/insts/mem.isa @@ -39,7 +39,8 @@ let {{ def loadStoreBaseWork(name, Name, imm, swp, codeBlobs, memFlags, - instFlags, base = 'Memory', execTemplateBase = ''): + instFlags, double, base = 'Memory', + execTemplateBase = ''): # Make sure flags are in lists (convert to lists if not). memFlags = makeList(memFlags) instFlags = makeList(instFlags) @@ -66,11 +67,19 @@ let {{ declareTemplate = SwapDeclare constructTemplate = SwapConstructor elif imm: - declareTemplate = LoadStoreImmDeclare - constructTemplate = LoadStoreImmConstructor + if double: + declareTemplate = LoadStoreDImmDeclare + constructTemplate = LoadStoreDImmConstructor + else: + declareTemplate = LoadStoreImmDeclare + constructTemplate = LoadStoreImmConstructor else: - declareTemplate = LoadStoreRegDeclare - constructTemplate = LoadStoreRegConstructor + if double: + declareTemplate = LoadStoreDRegDeclare + constructTemplate = LoadStoreDRegConstructor + else: + declareTemplate = LoadStoreRegDeclare + constructTemplate = LoadStoreRegConstructor # (header_output, decoder_output, decode_block, exec_output) return (declareTemplate.subst(iop), @@ -80,12 +89,13 @@ let {{ + completeAccTemplate.subst(iop)) def loadStoreBase(name, Name, imm, eaCode, accCode, memFlags, - instFlags, base = 'Memory', execTemplateBase = ''): + instFlags, double, base = 'Memory', + execTemplateBase = ''): codeBlobs = { "ea_code": eaCode, "memacc_code": accCode, "predicate_test": predicateTest } return loadStoreBaseWork(name, Name, imm, False, codeBlobs, memFlags, - instFlags, base, execTemplateBase) + instFlags, double, base, execTemplateBase) def SwapBase(name, Name, eaCode, preAccCode, postAccCode, memFlags, instFlags): @@ -94,7 +104,7 @@ let {{ "postacc_code": postAccCode, "predicate_test": predicateTest } return loadStoreBaseWork(name, Name, False, True, codeBlobs, memFlags, - instFlags, 'Swap', 'Swap') + instFlags, False, 'Swap', 'Swap') def memClassName(base, post, add, writeback, \ size=4, sign=False, user=False): diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa index 3349ba029..cf9eed74e 100644 --- a/src/arch/arm/isa/insts/str.isa +++ b/src/arch/arm/isa/insts/str.isa @@ -61,14 +61,15 @@ let {{ return memClassName("STORE_REGD", post, add, writeback, 4, False, False) - def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base): + def emitStore(name, Name, imm, eaCode, accCode, \ + memFlags, instFlags, base, double=False): global header_output, decoder_output, exec_output (newHeader, newDecoder, newExec) = loadStoreBase(name, Name, imm, eaCode, accCode, - memFlags, instFlags, + memFlags, instFlags, double, base, execTemplateBase = 'Store') header_output += newHeader @@ -139,12 +140,13 @@ let {{ eaCode += offset eaCode += ";" - accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' + accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryImm", post, writeback) + base = buildMemBase("MemoryDImm", post, writeback) - emitStore(name, Name, True, eaCode, accCode, [], [], base) + emitStore(name, Name, True, eaCode, accCode, \ + [], [], base, double=True) def buildDoubleRegStore(mnem, post, add, writeback): name = mnem @@ -162,12 +164,13 @@ let {{ eaCode += offset eaCode += ";" - accCode = 'Mem.ud = (Rdo.ud & mask(32)) | (Rde.ud << 32);' + accCode = 'Mem.ud = (Dest.ud & mask(32)) | (Dest2.ud << 32);' if writeback: accCode += "Base = Base %s;\n" % offset - base = buildMemBase("MemoryReg", post, writeback) + base = buildMemBase("MemoryDReg", post, writeback) - emitStore(name, Name, False, eaCode, accCode, [], [], base) + emitStore(name, Name, False, eaCode, accCode, \ + [], [], base, double=True) def buildStores(mnem, size=4, sign=False, user=False): buildImmStore(mnem, True, True, True, size, sign, user) diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 903982f29..0f3534385 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -90,6 +90,8 @@ def operands {{ #Abstracted integer reg operands 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, maybePCRead, maybePCWrite), + 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0, + maybePCRead, maybePCWrite), 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, maybePCRead, maybeIWPCWrite), 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, @@ -124,10 +126,6 @@ def operands {{ 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), - #Destination register for load/store double instructions - 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), - 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), - 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index e01470666..6e76b07c1 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -314,6 +314,27 @@ def template SwapDeclare {{ }; }}; +def template LoadStoreDImmDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + + /// Constructor. + %(class_name)s(ExtMachInst machInst, + uint32_t _dest, uint32_t _dest2, + uint32_t _base, bool _add, int32_t _imm); + + %(BasicExecDeclare)s + + %(InitiateAccDeclare)s + + %(CompleteAccDeclare)s + }; +}}; + def template LoadStoreImmDeclare {{ /** * Static instruction class for "%(mnemonic)s". @@ -334,6 +355,29 @@ def template LoadStoreImmDeclare {{ }; }}; +def template LoadStoreDRegDeclare {{ + /** + * Static instruction class for "%(mnemonic)s". + */ + class %(class_name)s : public %(base_class)s + { + public: + + /// Constructor. + %(class_name)s(ExtMachInst machInst, + uint32_t _dest, uint32_t _dest2, + uint32_t _base, bool _add, + int32_t _shiftAmt, uint32_t _shiftType, + uint32_t _index); + + %(BasicExecDeclare)s + + %(InitiateAccDeclare)s + + %(CompleteAccDeclare)s + }; +}}; + def template LoadStoreRegDeclare {{ /** * Static instruction class for "%(mnemonic)s". @@ -374,6 +418,18 @@ def template SwapConstructor {{ } }}; +def template LoadStoreDImmConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + uint32_t _dest, uint32_t _dest2, + uint32_t _base, bool _add, int32_t _imm) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + (IntRegIndex)_dest, (IntRegIndex)_dest2, + (IntRegIndex)_base, _add, _imm) + { + %(constructor)s; + } +}}; + def template LoadStoreImmConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) @@ -384,6 +440,20 @@ def template LoadStoreImmConstructor {{ } }}; +def template LoadStoreDRegConstructor {{ + inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, + int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + (IntRegIndex)_dest, (IntRegIndex)_dest2, + (IntRegIndex)_base, _add, + _shiftAmt, (ArmShiftType)_shiftType, + (IntRegIndex)_index) + { + %(constructor)s; + } +}}; + def template LoadStoreRegConstructor {{ inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, |