diff options
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/decoder/arm.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/decoder/thumb.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 45 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/uncond.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 54 |
5 files changed, 105 insertions, 5 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa index 9ab95b82f..4bd9d5cf4 100644 --- a/src/arch/arm/isa/decoder/arm.isa +++ b/src/arch/arm/isa/decoder/arm.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -114,6 +114,7 @@ format DataOp { 1: decode CPNUM { // 27-24=1110,4 ==1 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xe: McrMrc14::mcrMrc14(); 0xf: McrMrc15::mcrMrc15(); } // CPNUM (OP4 == 1) } //OPCODE_4 diff --git a/src/arch/arm/isa/decoder/thumb.isa b/src/arch/arm/isa/decoder/thumb.isa index f144e3003..f54cc728d 100644 --- a/src/arch/arm/isa/decoder/thumb.isa +++ b/src/arch/arm/isa/decoder/thumb.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -86,6 +86,7 @@ decode BIGTHUMB { 0x1: decode LTCOPROC { 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xe: McrMrc14::mcrMrc14(); 0xf: McrMrc15::mcrMrc15(); } } @@ -142,6 +143,7 @@ decode BIGTHUMB { 0x1: decode LTCOPROC { 0x1: M5ops::m5ops(); 0xa, 0xb: ShortFpTransfer::shortFpTransfer(); + 0xe: McrMrc14::mcrMrc14(); 0xf: McrMrc15::mcrMrc15(); } } diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 54482864a..3865cffe2 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -85,6 +85,49 @@ let {{ ''' decoder_output = ''' StaticInstPtr + decodeMcrMrc14(ExtMachInst machInst) + { + const uint32_t opc1 = bits(machInst, 23, 21); + const uint32_t crn = bits(machInst, 19, 16); + const uint32_t opc2 = bits(machInst, 7, 5); + const uint32_t crm = bits(machInst, 3, 0); + const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2); + const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); + + const bool isRead = bits(machInst, 20); + + switch (miscReg) { + case MISCREG_NOP: + return new NopInst(machInst); + case NUM_MISCREGS: + return new FailUnimplemented( + csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown", + crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(), + machInst); + default: + if (isRead) { + return new Mrc14(machInst, rt, (IntRegIndex)miscReg); + } else { + return new Mcr14(machInst, (IntRegIndex)miscReg, rt); + } + } + } + ''' +}}; + +def format McrMrc14() {{ + decode_block = ''' + return decodeMcrMrc14(machInst); + ''' +}}; + +let {{ + header_output = ''' + StaticInstPtr + decodeMcrMrc15(ExtMachInst machInst); + ''' + decoder_output = ''' + StaticInstPtr decodeMcrMrc15(ExtMachInst machInst) { const uint32_t opc1 = bits(machInst, 23, 21); diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa index 0ef113607..4a18a55bb 100644 --- a/src/arch/arm/isa/formats/uncond.isa +++ b/src/arch/arm/isa/formats/uncond.isa @@ -1,4 +1,4 @@ -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -269,6 +269,8 @@ def format ArmUnconditional() {{ if (bits(op1, 4) == 0) { if (CPNUM == 0xa || CPNUM == 0xb) { return decodeShortFpTransfer(machInst); + } else if (CPNUM == 0xe) { + return decodeMcrMrc14(machInst); } else if (CPNUM == 0xf) { return decodeMcrMrc15(machInst); } diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index d8ee5e88d..831920e1b 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -1,6 +1,6 @@ // -*- mode:c++ -*- -// Copyright (c) 2010 ARM Limited +// Copyright (c) 2010-2012 ARM Limited // All rights reserved // // The license below extends only to copyright in the software and shall @@ -626,6 +626,58 @@ let {{ decoder_output += RegRegImmImmOpConstructor.subst(bfiIop) exec_output += PredOpExecute.subst(bfiIop) + mrc14code = ''' + CPSR cpsr = Cpsr; + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } + Dest = MiscOp1; + ''' + + mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp", + { "code": mrc14code, + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc14Iop) + decoder_output += RegRegOpConstructor.subst(mrc14Iop) + exec_output += PredOpExecute.subst(mrc14Iop) + + + mcr14code = ''' + CPSR cpsr = Cpsr; + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } + MiscDest = Op1; + ''' + mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp", + { "code": mcr14code, + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) + header_output += RegRegOpDeclare.subst(mcr14Iop) + decoder_output += RegRegOpConstructor.subst(mcr14Iop) + exec_output += PredOpExecute.subst(mcr14Iop) + + mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp", + { "code": "Dest = MiscOp1;", + "predicate_test": predicateTest }, []) + header_output += RegRegOpDeclare.subst(mrc14UserIop) + decoder_output += RegRegOpConstructor.subst(mrc14UserIop) + exec_output += PredOpExecute.subst(mrc14UserIop) + + mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp", + { "code": "MiscDest = Op1", + "predicate_test": predicateTest }, + ["IsSerializeAfter","IsNonSpeculative"]) + header_output += RegRegOpDeclare.subst(mcr14UserIop) + decoder_output += RegRegOpConstructor.subst(mcr14UserIop) + exec_output += PredOpExecute.subst(mcr14UserIop) + mrc15code = ''' CPSR cpsr = Cpsr; if (cpsr.mode == MODE_USER) { |