diff options
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r-- | src/arch/arm/isa/formats/breakpoint.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/basic.isa | 3 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/branch.isa | 25 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/branch64.isa | 10 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/data64.isa | 20 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/macromem.isa | 37 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/mem.isa | 104 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/mem64.isa | 129 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 47 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/misc64.isa | 10 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/mult.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/neon.isa | 10 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/neon64.isa | 23 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/pred.isa | 6 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/vfp.isa | 10 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/vfp64.isa | 2 |
16 files changed, 245 insertions, 199 deletions
diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa index 4db470b1e..4f281e045 100644 --- a/src/arch/arm/isa/formats/breakpoint.isa +++ b/src/arch/arm/isa/formats/breakpoint.isa @@ -63,10 +63,10 @@ output header {{ flags[IsNonSpeculative] = true; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + generateDisassembly(Addr pc, const SymbolTable *symtab) const override; }; }}; diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index ebfddb0a6..1165a1e2a 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -50,7 +50,8 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(ExtMachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, + Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa index 54821e7c8..440adb4c5 100644 --- a/src/arch/arm/isa/templates/branch.isa +++ b/src/arch/arm/isa/templates/branch.isa @@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -72,8 +72,9 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; @@ -105,7 +106,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -135,7 +136,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -167,7 +168,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -178,9 +179,10 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -209,8 +211,9 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa index c55d20541..6eadf3c7c 100644 --- a/src/arch/arm/isa/templates/branch64.isa +++ b/src/arch/arm/isa/templates/branch64.isa @@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -63,7 +63,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -84,7 +84,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t imm, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -125,7 +125,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa index 85dde6bed..02c0fdd92 100644 --- a/src/arch/arm/isa/templates/data64.isa +++ b/src/arch/arm/isa/templates/data64.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -94,7 +94,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ArmExtendType _extendType, int32_t _shiftAmt); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -211,7 +211,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, uint8_t _defCc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -236,7 +236,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -261,7 +261,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index b0e3d29fd..37d0608c0 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -53,9 +53,10 @@ def template MicroMemDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -85,9 +86,10 @@ def template MicroMemPairDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, bool _up, uint8_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -134,9 +136,10 @@ def template MicroNeonMemDeclare {{ } } - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -154,7 +157,7 @@ def template MicroSetPCCPSRDeclare {{ IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -189,7 +192,7 @@ def template MicroIntDeclare {{ public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -251,7 +254,7 @@ def template MicroNeonMixDeclare {{ } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -304,7 +307,7 @@ def template MicroNeonMixLaneDeclare {{ } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -319,7 +322,7 @@ def template MicroIntMovDeclare {{ public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; def template MicroIntMovConstructor {{ @@ -350,7 +353,7 @@ def template MicroIntImmDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -390,7 +393,7 @@ def template MicroIntRegDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -412,7 +415,7 @@ def template MicroIntXERegDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, ArmExtendType _type, uint32_t _shiftAmt); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 38f5d2051..aa63d4b57 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -582,9 +582,10 @@ def template RfeDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -600,9 +601,10 @@ def template SrsDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -618,9 +620,10 @@ def template SwapDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -637,9 +640,10 @@ def template LoadStoreDImmDeclare {{ uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -656,9 +660,10 @@ def template StoreExDImmDeclare {{ uint32_t _result, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -674,12 +679,14 @@ def template LoadStoreImmDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -698,9 +705,10 @@ def template StoreExImmDeclare {{ uint32_t _result, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -719,9 +727,10 @@ def template StoreDRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -739,12 +748,14 @@ def template StoreRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -765,9 +776,10 @@ def template LoadDRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -785,12 +797,14 @@ def template LoadRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -808,12 +822,14 @@ def template LoadImmDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index a44a3cd25..bb8594cfe 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -259,12 +259,14 @@ def template DCStore64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; - - virtual void - annotateFault(ArmFault *fault) { + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; + + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -342,12 +344,14 @@ def template LoadStoreImm64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, int64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -364,12 +368,14 @@ def template LoadStoreImmU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -386,12 +392,14 @@ def template LoadStoreImmDU64Declare {{ int64_t _imm = 0, bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -410,9 +418,10 @@ def template StoreImmDEx64Declare {{ IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm = 0); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -427,12 +436,14 @@ def template LoadStoreReg64Declare {{ IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, ArmExtendType _type, uint32_t _shiftAmt); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -450,12 +461,14 @@ def template LoadStoreRegU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -470,12 +483,14 @@ def template LoadStoreRaw64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -490,12 +505,14 @@ def template LoadStoreEx64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -509,12 +526,14 @@ def template LoadStoreLit64Declare {{ /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -530,12 +549,14 @@ def template LoadStoreLitU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 6d63b8e14..e57b9e4af 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _sysM, bool _r); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t _sysM, bool _r); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -158,7 +158,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -185,7 +185,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -215,7 +215,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest, uint32_t imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -244,7 +244,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -268,7 +268,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -294,7 +294,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -321,7 +321,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -382,7 +382,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -412,7 +412,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -442,7 +442,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -472,7 +472,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -501,7 +501,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -531,7 +531,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -561,7 +561,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -591,7 +591,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -623,9 +623,10 @@ def template MiscRegRegImmMemOpDeclare {{ %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa index 3811cb56a..3c830c858 100644 --- a/src/arch/arm/isa/templates/misc64.isa +++ b/src/arch/arm/isa/templates/misc64.isa @@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst,uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -66,7 +66,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -117,7 +117,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa index 87d96f743..96c61fb28 100644 --- a/src/arch/arm/isa/templates/mult.isa +++ b/src/arch/arm/isa/templates/mult.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2, IntRegIndex _reg3); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index 5cde08dcf..35bd3865e 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -71,7 +71,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -97,7 +97,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -122,7 +122,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index 153933611..26e6d98b5 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -267,9 +267,10 @@ def template MicroNeonMemDeclare64 {{ %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -477,7 +478,7 @@ def template MicroNeonMixDeclare64 {{ %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -496,7 +497,7 @@ def template MicroNeonMixLaneDeclare64 {{ %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index d2060a7cd..dccdea60a 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -57,7 +57,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC=true); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -96,7 +96,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index c5765f21e..c0859e311 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -189,7 +189,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _cond, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa index 64932336f..f228356be 100644 --- a/src/arch/arm/isa/templates/vfp64.isa +++ b/src/arch/arm/isa/templates/vfp64.isa @@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; |