summaryrefslogtreecommitdiff
path: root/src/arch/arm/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r--src/arch/arm/isa/insts/misc.isa10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 09d27360e..c673372bb 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -174,6 +174,16 @@ let {{
decoder_output += RevOpConstructor.subst(rbitIop)
exec_output += PredOpExecute.subst(rbitIop)
+ clzCode = '''
+ Dest = (Op1 == 0) ? 32 : (31 - findMsbSet(Op1));
+ '''
+ clzIop = InstObjParams("clz", "ClzInst", "RevOp",
+ { "code": clzCode,
+ "predicate_test": predicateTest }, [])
+ header_output += RevOpDeclare.subst(clzIop)
+ decoder_output += RevOpConstructor.subst(clzIop)
+ exec_output += PredOpExecute.subst(clzIop)
+
ssatCode = '''
int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
int32_t res;