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-rw-r--r--src/arch/arm/isa/formats/breakpoint.isa2
-rw-r--r--src/arch/arm/isa/insts/fp.isa8
-rw-r--r--src/arch/arm/isa/templates/basic.isa17
-rw-r--r--src/arch/arm/isa/templates/branch.isa20
-rw-r--r--src/arch/arm/isa/templates/branch64.isa10
-rw-r--r--src/arch/arm/isa/templates/data64.isa20
-rw-r--r--src/arch/arm/isa/templates/macromem.isa42
-rw-r--r--src/arch/arm/isa/templates/mem.isa104
-rw-r--r--src/arch/arm/isa/templates/mem64.isa68
-rw-r--r--src/arch/arm/isa/templates/misc.isa40
-rw-r--r--src/arch/arm/isa/templates/misc64.isa4
-rw-r--r--src/arch/arm/isa/templates/mult.isa4
-rw-r--r--src/arch/arm/isa/templates/neon.isa10
-rw-r--r--src/arch/arm/isa/templates/neon64.isa24
-rw-r--r--src/arch/arm/isa/templates/pred.isa6
-rw-r--r--src/arch/arm/isa/templates/vfp.isa10
-rw-r--r--src/arch/arm/isa/templates/vfp64.isa2
17 files changed, 161 insertions, 230 deletions
diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa
index 69d6855e3..a22f2de7a 100644
--- a/src/arch/arm/isa/formats/breakpoint.isa
+++ b/src/arch/arm/isa/formats/breakpoint.isa
@@ -63,7 +63,7 @@ output header {{
flags[IsNonSpeculative] = true;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index dff906755..dcf5889fb 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -60,8 +60,6 @@ class VfpMacroRegRegOp : public VfpMacroOp
nextIdxs(_dest, _op1);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
@@ -96,8 +94,6 @@ class VfpMacroRegImmOp : public VfpMacroOp
nextIdxs(_dest);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
@@ -132,8 +128,6 @@ class VfpMacroRegRegImmOp : public VfpMacroOp
nextIdxs(_dest, _op1);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
@@ -168,8 +162,6 @@ class VfpMacroRegRegRegOp : public VfpMacroOp
nextIdxs(_dest, _op1, _op2);
}
}
-
- %(BasicExecPanic)s
};
template <class VfpOp>
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index c4c570bbe..ebfddb0a6 100644
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -40,11 +40,6 @@
//
// Authors: Stephen Hines
-// Declarations for execute() methods.
-def template BasicExecDeclare {{
- Fault execute(ExecContext *, Trace::InstRecord *) const;
-}};
-
// Basic instruction class declaration template.
def template BasicDeclare {{
/**
@@ -55,7 +50,7 @@ def template BasicDeclare {{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -108,13 +103,3 @@ def template BasicDecode {{
def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
-
-// Definitions of execute methods that panic.
-def template BasicExecPanic {{
-Fault execute(ExecContext *, Trace::InstRecord *) const
-{
- panic("Execute method called when it shouldn't!");
- // GCC < 4.3 fail to recognize the above panic as no return
- return NoFault;
-}
-}};
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 92c566726..54821e7c8 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -72,7 +72,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t _imm,
ConditionCode _condCode);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
/// Explicitly import the otherwise hidden branchTarget
@@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -135,7 +135,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
ConditionCode _condCode);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -167,7 +167,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1, IntRegIndex _op2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -178,11 +178,9 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1, IntRegIndex _op2);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -211,7 +209,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
int32_t imm, IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const;
/// Explicitly import the otherwise hidden branchTarget
diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa
index 241d12260..c55d20541 100644
--- a/src/arch/arm/isa/templates/branch64.isa
+++ b/src/arch/arm/isa/templates/branch64.isa
@@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -63,7 +63,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm,
ConditionCode _condCode);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -84,7 +84,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
int64_t imm, IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -125,7 +125,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa
index 7b0438a01..85dde6bed 100644
--- a/src/arch/arm/isa/templates/data64.isa
+++ b/src/arch/arm/isa/templates/data64.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -94,7 +94,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2,
ArmExtendType _extendType, int32_t _shiftAmt);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -211,7 +211,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
uint64_t _imm, ConditionCode _condCode, uint8_t _defCc);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -236,7 +236,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
IntRegIndex _op2, ConditionCode _condCode,
uint8_t _defCc);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -261,7 +261,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2,
ConditionCode _condCode);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index 05acb52eb..b0e3d29fd 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -53,9 +53,9 @@ def template MicroMemDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, bool _up,
uint8_t _imm);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -85,9 +85,9 @@ def template MicroMemPairDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
bool _up, uint8_t _imm);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -134,9 +134,9 @@ def template MicroNeonMemDeclare {{
}
}
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -154,7 +154,7 @@ def template MicroSetPCCPSRDeclare {{
IntRegIndex _ura,
IntRegIndex _urb,
IntRegIndex _urc);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -189,7 +189,7 @@ def template MicroIntDeclare {{
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -251,7 +251,7 @@ def template MicroNeonMixDeclare {{
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -304,7 +304,7 @@ def template MicroNeonMixLaneDeclare {{
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -319,7 +319,7 @@ def template MicroIntMovDeclare {{
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
def template MicroIntMovConstructor {{
@@ -350,7 +350,7 @@ def template MicroIntImmDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb,
int32_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -390,7 +390,7 @@ def template MicroIntRegDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
int32_t _shiftAmt, ArmShiftType _shiftType);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -412,7 +412,7 @@ def template MicroIntXERegDeclare {{
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
ArmExtendType _type, uint32_t _shiftAmt);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -448,7 +448,6 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
bool index, bool up, bool user, bool writeback, bool load,
uint32_t reglist);
- %(BasicExecPanic)s
};
}};
@@ -476,7 +475,6 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
- %(BasicExecPanic)s
};
}};
@@ -497,7 +495,6 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
bool load, IntRegIndex dest, IntRegIndex base,
IntRegIndex offset, ArmExtendType type, int64_t imm);
- %(BasicExecPanic)s
};
}};
@@ -519,7 +516,6 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
IntRegIndex dest, int64_t imm);
- %(BasicExecPanic)s
};
}};
@@ -542,7 +538,6 @@ class %(class_name)s : public %(base_class)s
bool exclusive, bool acrel, uint32_t imm,
AddrMode mode, IntRegIndex rn, IntRegIndex rt,
IntRegIndex rt2);
- %(BasicExecPanic)s
};
}};
@@ -567,7 +562,6 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, unsigned width,
RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
uint32_t size, uint32_t align, RegIndex rm);
- %(BasicExecPanic)s
};
}};
@@ -595,7 +589,6 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, bool all, unsigned width,
RegIndex rn, RegIndex vd, unsigned regs, unsigned inc,
uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0);
- %(BasicExecPanic)s
};
}};
@@ -626,7 +619,6 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
RegIndex vd, bool single, bool up, bool writeback,
bool load, uint32_t offset);
- %(BasicExecPanic)s
};
}};
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 44f6ea797..38f5d2051 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -582,11 +582,9 @@ def template RfeDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -602,11 +600,9 @@ def template SrsDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _regMode, int _mode, bool _wb);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -622,11 +618,9 @@ def template SwapDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -643,11 +637,9 @@ def template LoadStoreDImmDeclare {{
uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -664,11 +656,9 @@ def template StoreExDImmDeclare {{
uint32_t _result, uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -684,11 +674,9 @@ def template LoadStoreImmDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -710,11 +698,9 @@ def template StoreExImmDeclare {{
uint32_t _result, uint32_t _dest, uint32_t _base,
bool _add, int32_t _imm);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -733,11 +719,9 @@ def template StoreDRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -755,11 +739,9 @@ def template StoreRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -783,11 +765,9 @@ def template LoadDRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -805,11 +785,9 @@ def template LoadRegDeclare {{
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -830,11 +808,9 @@ def template LoadImmDeclare {{
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -843,14 +819,6 @@ def template LoadImmDeclare {{
};
}};
-def template InitiateAccDeclare {{
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
-}};
-
-def template CompleteAccDeclare {{
- Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
-}};
-
def template RfeConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb)
diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index fc922b330..ff4114898 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -258,9 +258,9 @@ def template DCStore64Declare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _base, IntRegIndex _dest, uint64_t _imm);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -340,9 +340,9 @@ def template LoadStoreImm64Declare {{
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _base, int64_t _imm);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -362,9 +362,9 @@ def template LoadStoreImmU64Declare {{
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -384,9 +384,9 @@ def template LoadStoreImmDU64Declare {{
int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -408,11 +408,9 @@ def template StoreImmDEx64Declare {{
IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
IntRegIndex _base, int64_t _imm = 0);
- %(BasicExecDeclare)s
-
- %(InitiateAccDeclare)s
-
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -427,9 +425,9 @@ def template LoadStoreReg64Declare {{
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -450,9 +448,9 @@ def template LoadStoreRegU64Declare {{
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -470,9 +468,9 @@ def template LoadStoreRaw64Declare {{
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _base);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -490,9 +488,9 @@ def template LoadStoreEx64Declare {{
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _base, IntRegIndex _result);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -509,9 +507,9 @@ def template LoadStoreLit64Declare {{
/// Constructor.
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
@@ -530,9 +528,9 @@ def template LoadStoreLitU64Declare {{
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
virtual void
annotateFault(ArmFault *fault) {
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index d661b4f18..0a23ba5d3 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
uint8_t _sysM, bool _r);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
uint8_t _sysM, bool _r);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -158,7 +158,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -185,7 +185,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -215,7 +215,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
MiscRegIndex _dest, uint32_t imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -244,7 +244,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -268,7 +268,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -294,7 +294,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -321,7 +321,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
IntRegIndex _op2, IntRegIndex _op3);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -382,7 +382,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -412,7 +412,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -442,7 +442,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
MiscRegIndex _dest, IntRegIndex _op1,
uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -472,7 +472,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, MiscRegIndex _op1,
uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -501,7 +501,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -531,7 +531,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -561,7 +561,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -591,7 +591,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index 3ccb3dc17..842997902 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -46,7 +46,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -72,7 +72,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
IntRegIndex _op2, uint64_t _imm);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa
index 0099e5c9d..87d96f743 100644
--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
IntRegIndex _reg1, IntRegIndex _reg2);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _reg0, IntRegIndex _reg1,
IntRegIndex _reg2, IntRegIndex _reg3);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index c1ec74135..5cde08dcf 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -71,7 +71,7 @@ class %(class_name)s : public %(base_class)s
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -97,7 +97,7 @@ class %(class_name)s : public %(base_class)s
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -122,7 +122,7 @@ class %(class_name)s : public %(base_class)s
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s
}
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa
index f11ee91d4..153933611 100644
--- a/src/arch/arm/isa/templates/neon64.isa
+++ b/src/arch/arm/isa/templates/neon64.isa
@@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -267,9 +267,9 @@ def template MicroNeonMemDeclare64 {{
%(constructor)s;
}
- %(BasicExecDeclare)s
- %(InitiateAccDeclare)s
- %(CompleteAccDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -420,7 +420,6 @@ def template VMemMultDeclare64 {{
%(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd,
RegIndex rm, uint8_t eSize, uint8_t dataSize,
uint8_t numStructElems, uint8_t numRegs, bool wb);
- %(BasicExecPanic)s
};
}};
@@ -433,7 +432,6 @@ def template VMemSingleDeclare64 {{
RegIndex rm, uint8_t eSize, uint8_t dataSize,
uint8_t numStructElems, uint8_t index, bool wb,
bool replicate = false);
- %(BasicExecPanic)s
};
}};
@@ -479,7 +477,7 @@ def template MicroNeonMixDeclare64 {{
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -498,7 +496,7 @@ def template MicroNeonMixLaneDeclare64 {{
%(constructor)s;
}
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index fb0a404cb..d2060a7cd 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -57,7 +57,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -96,7 +96,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
ArmShiftType _shiftType);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index d94f4652a..c5765f21e 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
VfpMicroMode mode = VfpNotAMicroop);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -189,7 +189,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
VfpMicroMode mode = VfpNotAMicroop);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
@@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
ConditionCode _cond,
VfpMicroMode mode = VfpNotAMicroop);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa
index ea76472f5..64932336f 100644
--- a/src/arch/arm/isa/templates/vfp64.isa
+++ b/src/arch/arm/isa/templates/vfp64.isa
@@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop);
- %(BasicExecDeclare)s
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 17:58:35 +0000