diff options
Diffstat (limited to 'src/arch/arm/isa')
-rw-r--r-- | src/arch/arm/isa/formats/breakpoint.isa | 3 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/unimp.isa | 6 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/branch.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/branch64.isa | 4 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 24 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/fp.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 83 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc64.isa | 11 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 13 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon64.isa | 3 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon64_mem.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 3 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/mem64.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/neon.isa | 6 | ||||
-rw-r--r-- | src/arch/arm/isa/templates/vfp.isa | 30 |
16 files changed, 124 insertions, 72 deletions
diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa index 9795d864d..c55cdf6f6 100644 --- a/src/arch/arm/isa/formats/breakpoint.isa +++ b/src/arch/arm/isa/formats/breakpoint.isa @@ -83,7 +83,8 @@ output exec {{ Breakpoint::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const { - return new PrefetchAbort(xc->pcState().pc(), ArmFault::DebugEvent); + return std::make_shared<PrefetchAbort>(xc->pcState().pc(), + ArmFault::DebugEvent); } }}; diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa index bdfb0b255..8496237c2 100644 --- a/src/arch/arm/isa/formats/unimp.isa +++ b/src/arch/arm/isa/formats/unimp.isa @@ -176,7 +176,8 @@ output exec {{ FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } Fault @@ -196,7 +197,8 @@ output exec {{ FlushPipeInst::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const { - return new FlushPipe(); + Fault fault = std::make_shared<FlushPipe>(); + return fault; } }}; diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa index 47fd4e805..086abacb7 100644 --- a/src/arch/arm/isa/insts/branch.isa +++ b/src/arch/arm/isa/insts/branch.isa @@ -157,7 +157,7 @@ let {{ if (ArmSystem::haveVirtualization(xc->tcBase()) && hstr.tjdbx && !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { - fault = new HypervisorTrap(machInst, op1, EC_TRAPPED_BXJ); + fault = std::make_shared<HypervisorTrap>(machInst, op1, EC_TRAPPED_BXJ); } IWNPC = Op1; ''' diff --git a/src/arch/arm/isa/insts/branch64.isa b/src/arch/arm/isa/insts/branch64.isa index 89cee6c22..265eee9b6 100644 --- a/src/arch/arm/isa/insts/branch64.isa +++ b/src/arch/arm/isa/insts/branch64.isa @@ -115,7 +115,9 @@ let {{ newPc = xc->tcBase()->readMiscReg(MISCREG_ELR_EL1); break; default: - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, + false, + mnemonic); break; } if (spsr.width && (newPc & mask(2))) { diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 8ec446d16..cb5671b1e 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -294,28 +294,33 @@ let {{ flat_idx == MISCREG_DC_CVAC_Xt || flat_idx == MISCREG_DC_CIVAC_Xt ) - return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, + return std::make_shared<UndefinedInstruction>( + machInst, 0, EC_TRAPPED_MSR_MRS_64, mnemonic); - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } // Check for traps to supervisor (FP/SIMD regs) if (el <= EL1 && msrMrs64TrapToSup(flat_idx, el, Cpacr64)) - return new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP); + return std::make_shared<SupervisorTrap>(machInst, 0x1E00000, + EC_TRAPPED_SIMD_FP); bool is_vfp_neon = false; // Check for traps to hypervisor if ((ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) && msrMrs64TrapToHyp(flat_idx, %s, CptrEl264, Hcr64, &is_vfp_neon)) { - return new HypervisorTrap(machInst, is_vfp_neon ? 0x1E00000 : imm, + return std::make_shared<HypervisorTrap>( + machInst, is_vfp_neon ? 0x1E00000 : imm, is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64); } // Check for traps to secure monitor if ((ArmSystem::haveSecurity(xc->tcBase()) && el <= EL3) && msrMrs64TrapToMon(flat_idx, CptrEl364, el, &is_vfp_neon)) { - return new SecureMonitorTrap(machInst, + return std::make_shared<SecureMonitorTrap>( + machInst, is_vfp_neon ? 0x1E00000 : imm, is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64); } @@ -388,7 +393,8 @@ let {{ if (!canWriteAArch64SysReg( (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), Scr64, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } MiscDest_ud = imm; ''', optArgs = ["IsSerializeAfter", "IsNonSpeculative"]) @@ -397,7 +403,8 @@ let {{ if (!canWriteAArch64SysReg( (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), Scr64, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, + return std::make_shared<UndefinedInstruction>( + machInst, 0, EC_TRAPPED_MSR_MRS_64, mnemonic); } CPSR cpsr = Cpsr; @@ -409,7 +416,8 @@ let {{ if (!canWriteAArch64SysReg( (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), Scr64, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, + return std::make_shared<UndefinedInstruction>( + machInst, 0, EC_TRAPPED_MSR_MRS_64, mnemonic); } CPSR cpsr = Cpsr; diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index 60f030c3d..9a7f3f8a0 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -234,7 +234,7 @@ let {{ break; } if (hypTrap) { - return new HypervisorTrap(machInst, imm, + return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP10_MRC_VMRS); } } diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 41060ff01..8c1b26808 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -620,7 +620,7 @@ let {{ 'MicroIntImmXOp', ''' if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) && SPAlignmentCheckEnabled(xc->tcBase())) { - return new SPAlignmentFault(); + return std::make_shared<SPAlignmentFault>(); } XURa = XURb + imm; ''', ['IsMicroop']) diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 00c907acd..5403ddc8d 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -40,7 +40,7 @@ let {{ svcCode = ''' - fault = new SupervisorCall(machInst, imm); + fault = std::make_shared<SupervisorCall>(machInst, imm); ''' svcIop = InstObjParams("svc", "Svc", "ImmOp", @@ -59,12 +59,13 @@ let {{ if ((cpsr.mode != MODE_USER) && FullSystem) { if (ArmSystem::haveVirtualization(xc->tcBase()) && !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.tsc) { - fault = new HypervisorTrap(machInst, 0, EC_SMC_TO_HYP); + fault = std::make_shared<HypervisorTrap>(machInst, 0, + EC_SMC_TO_HYP); } else { if (scr.scd) { fault = disabledFault(); } else { - fault = new SecureMonitorCall(machInst); + fault = std::make_shared<SecureMonitorCall>(machInst); } } } else { @@ -90,7 +91,7 @@ let {{ (ArmSystem::haveSecurity(xc->tcBase()) && (!scr.ns || !scr.hce))) { fault = disabledFault(); } else { - fault = new HypervisorCall(machInst, imm); + fault = std::make_shared<HypervisorCall>(machInst, imm); } ''' @@ -179,7 +180,8 @@ let {{ Dest = xc->readMiscReg(regIdx); } } else { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } ''' mrsBankedRegIop = InstObjParams("mrs", "MrsBankedReg", "MrsOp", @@ -210,7 +212,8 @@ let {{ xc->setMiscReg(regIdx, Op1); } } else { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } ''' msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp", @@ -618,7 +621,7 @@ let {{ decoder_output += RegRegRegRegOpConstructor.subst(usada8Iop) exec_output += PredOpExecute.subst(usada8Iop) - bkptCode = 'return new PrefetchAbort(PC, ArmFault::DebugEvent);\n' + bkptCode = 'return std::make_shared<PrefetchAbort>(PC, ArmFault::DebugEvent);\n' bkptIop = InstObjParams("bkpt", "BkptInst", "PredOp", bkptCode) header_output += BasicDeclare.subst(bkptIop) decoder_output += BasicConstructor.subst(bkptIop) @@ -650,15 +653,18 @@ let {{ PseudoInst::quiesceSkip(tc); } else if (cpsr.el == EL0 && !sctlr.ntwe) { PseudoInst::quiesceSkip(tc); - fault = new SupervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE); + fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00001, + EC_TRAPPED_WFI_WFE); } else if (ArmSystem::haveVirtualization(tc) && !inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP) && hcr.twe) { PseudoInst::quiesceSkip(tc); - fault = new HypervisorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE); + fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00001, + EC_TRAPPED_WFI_WFE); } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twe) { PseudoInst::quiesceSkip(tc); - fault = new SecureMonitorTrap(machInst, 0x1E00001, EC_TRAPPED_WFI_WFE); + fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00001, + EC_TRAPPED_WFI_WFE); } else { PseudoInst::quiesce(tc); } @@ -691,14 +697,17 @@ let {{ PseudoInst::quiesceSkip(tc); } else if (cpsr.el == EL0 && !sctlr.ntwi) { PseudoInst::quiesceSkip(tc); - fault = new SupervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE); + fault = std::make_shared<SupervisorTrap>(machInst, 0x1E00000, + EC_TRAPPED_WFI_WFE); } else if (ArmSystem::haveVirtualization(tc) && hcr.twi && (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr)) { PseudoInst::quiesceSkip(tc); - fault = new HypervisorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE); + fault = std::make_shared<HypervisorTrap>(machInst, 0x1E00000, + EC_TRAPPED_WFI_WFE); } else if (ArmSystem::haveSecurity(tc) && cpsr.el != EL3 && scr.twi) { PseudoInst::quiesceSkip(tc); - fault = new SecureMonitorTrap(machInst, 0x1E00000, EC_TRAPPED_WFI_WFE); + fault = std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000, + EC_TRAPPED_WFI_WFE); } else { PseudoInst::quiesce(tc); } @@ -750,7 +759,7 @@ let {{ decoder_output += BasicConstructor.subst(itIop) exec_output += PredOpExecute.subst(itIop) unknownCode = ''' - return new UndefinedInstruction(machInst, true); + return std::make_shared<UndefinedInstruction>(machInst, true); ''' unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ { "code": unknownCode, @@ -804,11 +813,13 @@ let {{ mrc14code = ''' MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1); if (!canReadCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } if (mcrMrc14TrapToHyp((const MiscRegIndex) op1, Hcr, Cpsr, Scr, Hdcr, Hstr, Hcptr, imm)) { - return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC); + return std::make_shared<HypervisorTrap>(machInst, imm, + EC_TRAPPED_CP14_MCR_MRC); } Dest = MiscOp1; ''' @@ -824,11 +835,13 @@ let {{ mcr14code = ''' MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest); if (!canWriteCoprocReg(miscReg, Scr, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } if (mcrMrc14TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, Hcptr, imm)) { - return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP14_MCR_MRC); + return std::make_shared<HypervisorTrap>(machInst, imm, + EC_TRAPPED_CP14_MCR_MRC); } MiscDest = Op1; ''' @@ -852,10 +865,12 @@ let {{ // the register is accessable, in other modes we trap if only if the register // IS accessable. if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr, Cpsr))) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } if (hypTrap) { - return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); + return std::make_shared<HypervisorTrap>(machInst, imm, + EC_TRAPPED_CP15_MCR_MRC); } Dest = MiscNsBankedOp1; ''' @@ -880,10 +895,12 @@ let {{ // the register is accessable, in other modes we trap if only if the register // IS accessable. if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } if (hypTrap) { - return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); + return std::make_shared<HypervisorTrap>(machInst, imm, + EC_TRAPPED_CP15_MCR_MRC); } MiscNsBankedDest = Op1; ''' @@ -907,10 +924,12 @@ let {{ // the register is accessable, in other modes we trap if only if the register // IS accessable. if (!canRead && !(hypTrap && !inUserMode(Cpsr) && !inSecureState(Scr, Cpsr))) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } if (hypTrap) { - return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC); + return std::make_shared<HypervisorTrap>(machInst, imm, + EC_TRAPPED_CP15_MCRR_MRRC); } Dest = bits(MiscNsBankedOp164, 63, 32); Dest2 = bits(MiscNsBankedOp164, 31, 0); @@ -934,10 +953,12 @@ let {{ // the register is accessable, in other modes we trap if only if the register // IS accessable. if (!canWrite & !(hypTrap & !inUserMode(Cpsr) & !inSecureState(Scr, Cpsr))) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } if (hypTrap) { - return new HypervisorTrap(machInst, imm, EC_TRAPPED_CP15_MCRR_MRRC); + return std::make_shared<HypervisorTrap>(machInst, imm, + EC_TRAPPED_CP15_MCRR_MRRC); } MiscNsBankedDest64 = ((uint64_t) Op1 << 32) | Op2; ''' @@ -998,10 +1019,10 @@ let {{ // If the barrier is due to a CP15 access check for hyp traps if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr, Hdcr, Hstr, Hcptr, imm)) { - return new HypervisorTrap(machInst, imm, + return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } - fault = new FlushPipe; + fault = std::make_shared<FlushPipe>(); ''' isbIop = InstObjParams("isb", "Isb", "ImmOp", {"code": isbCode, @@ -1015,10 +1036,10 @@ let {{ // If the barrier is due to a CP15 access check for hyp traps if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr, Hdcr, Hstr, Hcptr, imm)) { - return new HypervisorTrap(machInst, imm, + return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } - fault = new FlushPipe; + fault = std::make_shared<FlushPipe>(); ''' dsbIop = InstObjParams("dsb", "Dsb", "ImmOp", {"code": dsbCode, @@ -1032,7 +1053,7 @@ let {{ // If the barrier is due to a CP15 access check for hyp traps if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr, Hdcr, Hstr, Hcptr, imm)) { - return new HypervisorTrap(machInst, imm, + return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } ''' diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index 6ebbcc2ba..e063813c7 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -39,7 +39,7 @@ let {{ svcCode = ''' - fault = new SupervisorCall(machInst, bits(machInst, 20, 5)); + fault = std::make_shared<SupervisorCall>(machInst, bits(machInst, 20, 5)); ''' svcIop = InstObjParams("svc", "Svc64", "ArmStaticInst", @@ -57,7 +57,7 @@ let {{ if (!ArmSystem::haveSecurity(xc->tcBase()) || inUserMode(cpsr) || scr.smd) { fault = disabledFault(); } else { - fault = new SecureMonitorCall(machInst); + fault = std::make_shared<SecureMonitorCall>(machInst); } ''' @@ -112,7 +112,7 @@ let {{ subst("RegRegRegImmOp64", extrIop); unknownCode = ''' - return new UndefinedInstruction(machInst, true); + return std::make_shared<UndefinedInstruction>(machInst, true); ''' unknown64Iop = InstObjParams("unknown", "Unknown64", "UnknownOp64", unknownCode) @@ -121,13 +121,14 @@ let {{ exec_output += BasicExecute.subst(unknown64Iop) isbIop = InstObjParams("isb", "Isb64", "ArmStaticInst", - "fault = new FlushPipe;", ['IsSerializeAfter']) + "fault = std::make_shared<FlushPipe>();", + ['IsSerializeAfter']) header_output += BasicDeclare.subst(isbIop) decoder_output += BasicConstructor64.subst(isbIop) exec_output += BasicExecute.subst(isbIop) dsbIop = InstObjParams("dsb", "Dsb64", "ArmStaticInst", - "fault = new FlushPipe;", + "fault = std::make_shared<FlushPipe>();", ['IsMemBarrier', 'IsSerializeAfter']) header_output += BasicDeclare.subst(dsbIop) decoder_output += BasicConstructor64.subst(dsbIop) diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 166176602..2f1e41f3e 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1372,7 +1372,8 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { - fault = new UndefinedInstruction(machInst, false, mnemonic); + fault = std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -1423,7 +1424,8 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { - fault = new UndefinedInstruction(machInst, false, mnemonic); + fault = std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -1472,7 +1474,8 @@ let {{ readDestCode = 'destReg = destRegs[i];' eWalkCode += ''' if (imm < 0 && imm >= eCount) { - fault = new UndefinedInstruction(machInst, false, mnemonic); + fault = std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } else { for (unsigned i = 0; i < rCount; i++) { FloatReg srcReg1 = srcRegs1[i]; @@ -3808,7 +3811,9 @@ let {{ } else { index -= eCount; if (index >= eCount) { - fault = new UndefinedInstruction(machInst, false, mnemonic); + fault = std::make_shared<UndefinedInstruction>(machInst, + false, + mnemonic); } else { destReg.elements[i] = srcReg2.elements[index]; } diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index bbe57bdfa..f6565efe5 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -1073,7 +1073,8 @@ let {{ } else { index -= eCount; if (index >= eCount) { - fault = new UndefinedInstruction(machInst, false, mnemonic); + fault = std::make_shared<UndefinedInstruction>( + machInst, false, mnemonic); } else { destReg.elements[i] = srcReg2.elements[index]; } diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa index 91fb4fa34..af31d959e 100644 --- a/src/arch/arm/isa/insts/neon64_mem.isa +++ b/src/arch/arm/isa/insts/neon64_mem.isa @@ -49,7 +49,7 @@ let {{ SPAlignmentCheckCodeNeon = ''' if (baseIsSP && bits(XURa, 3, 0) && SPAlignmentCheckEnabled(xc->tcBase())) { - return new SPAlignmentFault(); + return std::make_shared<SPAlignmentFault>(); } ''' eaCode = SPAlignmentCheckCodeNeon + ''' diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index f2ceed28e..4eac18e4c 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -73,7 +73,8 @@ let {{ swpPreAccCode = ''' if (!((SCTLR)Sctlr).sw) { - return new UndefinedInstruction(machInst, false, mnemonic); + return std::make_shared<UndefinedInstruction>(machInst, false, + mnemonic); } ''' diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index aa5b8f6b8..3d6cadb5d 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -41,7 +41,7 @@ let {{ SPAlignmentCheckCode = ''' if (baseIsSP && bits(XBase, 3, 0) && SPAlignmentCheckEnabled(xc->tcBase())) { - return new SPAlignmentFault(); + return std::make_shared<SPAlignmentFault>(); } ''' }}; diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index c437f7e13..45df741e7 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -49,11 +49,13 @@ let {{ if (trapEnCheck) { CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { - return new UndefinedInstruction(machInst, issEnCheck, + return std::make_shared<UndefinedInstruction>( + machInst, issEnCheck, EC_TRAPPED_HCPTR); } else { if (!inSecureState(Scr, Cpsr)) { - return new HypervisorTrap(machInst, issEnCheck, + return std::make_shared<HypervisorTrap>( + machInst, issEnCheck, EC_TRAPPED_HCPTR); } } diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index 45be8a5f3..4da00e8d5 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -48,11 +48,13 @@ let {{ if (trapEnCheck) { CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { - return new UndefinedInstruction(machInst, issEnCheck, + return std::make_shared<UndefinedInstruction>( + machInst, issEnCheck, EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { - return new HypervisorTrap(machInst, issEnCheck, + return std::make_shared<HypervisorTrap>( + machInst, issEnCheck, EC_TRAPPED_HCPTR); } } @@ -63,20 +65,20 @@ let {{ CPSR cpsrEnCheck = Cpsr; ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsrEnCheck.el; if (!vfpNeon64Enabled(Cpacr64, el)) - return new SupervisorTrap(machInst, 0x1E00000, + return std::make_shared<SupervisorTrap>(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP); if (ArmSystem::haveVirtualization(xc->tcBase()) && el <= EL2) { HCPTR cptrEnCheck = xc->tcBase()->readMiscReg(MISCREG_CPTR_EL2); if (cptrEnCheck.tfp) - return new HypervisorTrap(machInst, 0x1E00000, + return std::make_shared<HypervisorTrap>(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP); } if (ArmSystem::haveSecurity(xc->tcBase())) { HCPTR cptrEnCheck = xc->tcBase()->readMiscReg(MISCREG_CPTR_EL3); if (cptrEnCheck.tfp) - return new SecureMonitorTrap(machInst, 0x1E00000, + return std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000, EC_TRAPPED_SIMD_FP); } ''' @@ -95,11 +97,13 @@ let {{ if (trapEnCheck) { CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { - return new UndefinedInstruction(machInst, issEnCheck, + return std::make_shared<UndefinedInstruction>( + machInst, issEnCheck, EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { - return new HypervisorTrap(machInst, issEnCheck, + return std::make_shared<HypervisorTrap>( + machInst, issEnCheck, EC_TRAPPED_HCPTR); } } @@ -121,11 +125,13 @@ let {{ if (trapEnCheck) { CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { - return new UndefinedInstruction(machInst, issEnCheck, + return std::make_shared<UndefinedInstruction>( + machInst, issEnCheck, EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { - return new HypervisorTrap(machInst, issEnCheck, + return std::make_shared<HypervisorTrap>( + machInst, issEnCheck, EC_TRAPPED_HCPTR); } } @@ -141,11 +147,13 @@ let {{ if (trapEnCheck) { CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { - return new UndefinedInstruction(machInst, issEnCheck, + return std::make_shared<UndefinedInstruction>( + machInst, issEnCheck, EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { - return new HypervisorTrap(machInst, issEnCheck, + return std::make_shared<HypervisorTrap>( + machInst, issEnCheck, EC_TRAPPED_HCPTR); } } |