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-rw-r--r--src/arch/arm/isa/formats/misc.isa2
-rw-r--r--src/arch/arm/isa/formats/unimp.isa30
2 files changed, 31 insertions, 1 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 884d93066..2d47c286f 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -111,7 +111,7 @@ let {{
return new WarnUnimplemented(
isRead ? "mrc dcimvac" : "mcr dcimvac", machInst);
case MISCREG_DCCMVAC:
- return new WarnUnimplemented(
+ return new FlushPipeInst(
isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
case MISCREG_DCCMVAU:
return new WarnUnimplemented(
diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa
index a746f8a7b..a0e0afd32 100644
--- a/src/arch/arm/isa/formats/unimp.isa
+++ b/src/arch/arm/isa/formats/unimp.isa
@@ -101,6 +101,22 @@ output header {{
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+
+ class FlushPipeInst : public ArmStaticInst
+ {
+ public:
+ FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
+ {
+ flags[IsNonSpeculative] = true;
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+ };
}};
output decoder {{
@@ -117,6 +133,13 @@ output decoder {{
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
+
+ std::string
+ FlushPipeInst::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return csprintf("%-10s (pipe flush)", mnemonic);
+ }
}};
output exec {{
@@ -142,6 +165,13 @@ output exec {{
return NoFault;
}
+
+ Fault
+ FlushPipeInst::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ return new FlushPipe();
+ }
}};