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-rw-r--r--src/arch/arm/isa/insts/m5ops.isa7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index a157b414c..da2e10886 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -190,12 +190,15 @@ let {{
exec_output += PredOpExecute.subst(loadsymbolIop)
initparamCode = '''
- Rt = PseudoInst::initParam(xc->tcBase());
+ uint64_t ip_val = PseudoInst::initParam(xc->tcBase());
+ R0 = bits(ip_val, 31, 0);
+ R1 = bits(ip_val, 63, 32);
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
{ "code": initparamCode,
- "predicate_test": predicateTest })
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
header_output += BasicDeclare.subst(initparamIop)
decoder_output += BasicConstructor.subst(initparamIop)
exec_output += PredOpExecute.subst(initparamIop)