diff options
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/fp.isa | 12 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/crypto.isa | 15 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa index 26abc659f..77a33e6fe 100644 --- a/src/arch/arm/isa/formats/fp.isa +++ b/src/arch/arm/isa/formats/fp.isa @@ -1476,6 +1476,18 @@ let {{ case 0x5: return decodeNeonUTwoMiscSReg<NVpaddlD, NVpaddlQ>( q, size, machInst, vd, vm); + case 0x6: + if (q == 0) { + return new AESE(machInst, vd, vd, vm); + } else { + return new AESD(machInst, vd, vd, vm); + } + case 0x7: + if (q == 0) { + return new AESMC(machInst, vd, vm); + } else { + return new AESIMC(machInst, vd, vm); + } case 0x8: return decodeNeonSTwoMiscReg<NVclsD, NVclsQ>( q, size, machInst, vd, vm); diff --git a/src/arch/arm/isa/insts/crypto.isa b/src/arch/arm/isa/insts/crypto.isa index cdc0293a4..20ba4c486 100644 --- a/src/arch/arm/isa/insts/crypto.isa +++ b/src/arch/arm/isa/insts/crypto.isa @@ -136,6 +136,11 @@ let {{ decoder_output += RegRegImmOpConstructor.subst(cryptoiop) exec_output += CryptoPredOpExecute.subst(cryptoiop) + aeseCode = "crypto.aesEncrypt(output, input, input2);" + aesdCode = "crypto.aesDecrypt(output, input, input2);" + aesmcCode = "crypto.aesMixColumns(output, input);" + aesimcCode = "crypto.aesInvMixColumns(output, input);" + sha1_cCode = "crypto.sha1C(output, input, input2);" sha1_pCode = "crypto.sha1P(output, input, input2);" sha1_mCode = "crypto.sha1M(output, input, input2);" @@ -148,6 +153,16 @@ let {{ sha256_su0Code = "crypto.sha256Su0(output, input);" sha256_su1Code = "crypto.sha256Su1(output, input, input2);" + aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 } + cryptoRegRegRegInst("aese", "AESE", "SimdAesOp", + aes_enabled, aeseCode) + cryptoRegRegRegInst("aesd", "AESD", "SimdAesOp", + aes_enabled, aesdCode) + cryptoRegRegInst("aesmc", "AESMC", "SimdAesMixOp", + aes_enabled, aesmcCode) + cryptoRegRegInst("aesimc", "AESIMC", "SimdAesMixOp", + aes_enabled, aesimcCode) + sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 } cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp", sha1_enabled, sha1_cCode) |