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-rw-r--r--src/arch/arm/isa/insts/misc.isa3
-rw-r--r--src/arch/arm/isa/templates/misc.isa3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index f2a80a111..5742f84ab 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -671,7 +671,8 @@ let {{
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
- unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLEAR_LL |
+ ArmISA::TLB::AlignWord | Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
'''
clrexIop = InstObjParams("clrex", "Clrex","PredOp",
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 46af3f5b1..f8dac05f8 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -367,7 +367,8 @@ def template ClrexInitiateAcc {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
- unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLEAR_LL |
+ ArmISA::TLB::AlignWord | Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
}
} else {