diff options
Diffstat (limited to 'src/arch/arm/isa')
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 12 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/misc.isa | 60 |
3 files changed, 68 insertions, 8 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 0ba114e86..7d3865104 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -214,8 +214,8 @@ let {{ if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) { if (isRead) - return new Mrc15(machInst, rt, (IntRegIndex)miscReg, iss); - return new Mcr15(machInst, (IntRegIndex)miscReg, rt, iss); + return new Mrc15(machInst, rt, miscReg, iss); + return new Mcr15(machInst, miscReg, rt, iss); } else { return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst, csprintf("%s %s", isRead ? "mrc" : "mcr", diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 76fc1fbed..00c907acd 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -860,11 +860,11 @@ let {{ Dest = MiscNsBankedOp1; ''' - mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegImmOp", + mrc15Iop = InstObjParams("mrc", "Mrc15", "RegMiscRegImmOp", { "code": mrc15code, "predicate_test": predicateTest }, []) - header_output += RegRegImmOpDeclare.subst(mrc15Iop) - decoder_output += RegRegImmOpConstructor.subst(mrc15Iop) + header_output += RegMiscRegImmOpDeclare.subst(mrc15Iop) + decoder_output += RegMiscRegImmOpConstructor.subst(mrc15Iop) exec_output += PredOpExecute.subst(mrc15Iop) @@ -887,12 +887,12 @@ let {{ } MiscNsBankedDest = Op1; ''' - mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegImmOp", + mcr15Iop = InstObjParams("mcr", "Mcr15", "MiscRegRegImmOp", { "code": mcr15code, "predicate_test": predicateTest }, ["IsSerializeAfter","IsNonSpeculative"]) - header_output += RegRegImmOpDeclare.subst(mcr15Iop) - decoder_output += RegRegImmOpConstructor.subst(mcr15Iop) + header_output += MiscRegRegImmOpDeclare.subst(mcr15Iop) + decoder_output += MiscRegRegImmOpConstructor.subst(mcr15Iop) exec_output += PredOpExecute.subst(mcr15Iop) diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index c3866a51f..5cd4637a6 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -433,6 +433,66 @@ def template RegRegImmOpConstructor {{ } }}; +def template MiscRegRegImmOpDeclare {{ +class %(class_name)s : public %(base_class)s +{ + protected: + public: + // Constructor + %(class_name)s(ExtMachInst machInst, + MiscRegIndex _dest, IntRegIndex _op1, + uint64_t _imm); + %(BasicExecDeclare)s +}; +}}; + +def template MiscRegRegImmOpConstructor {{ + %(class_name)s::%(class_name)s(ExtMachInst machInst, + MiscRegIndex _dest, + IntRegIndex _op1, + uint64_t _imm) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _dest, _op1, _imm) + { + %(constructor)s; + if (!(condCode == COND_AL || condCode == COND_UC)) { + for (int x = 0; x < _numDestRegs; x++) { + _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; + } + } + } +}}; + +def template RegMiscRegImmOpDeclare {{ +class %(class_name)s : public %(base_class)s +{ + protected: + public: + // Constructor + %(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, MiscRegIndex _op1, + uint64_t _imm); + %(BasicExecDeclare)s +}; +}}; + +def template RegMiscRegImmOpConstructor {{ + %(class_name)s::%(class_name)s(ExtMachInst machInst, + IntRegIndex _dest, + MiscRegIndex _op1, + uint64_t _imm) + : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, + _dest, _op1, _imm) + { + %(constructor)s; + if (!(condCode == COND_AL || condCode == COND_UC)) { + for (int x = 0; x < _numDestRegs; x++) { + _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; + } + } + } +}}; + def template RegImmImmOpDeclare {{ class %(class_name)s : public %(base_class)s { |