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Diffstat (limited to 'src/arch/arm/kvm/base_cpu.cc')
-rw-r--r--src/arch/arm/kvm/base_cpu.cc35
1 files changed, 23 insertions, 12 deletions
diff --git a/src/arch/arm/kvm/base_cpu.cc b/src/arch/arm/kvm/base_cpu.cc
index e25112cae..765965092 100644
--- a/src/arch/arm/kvm/base_cpu.cc
+++ b/src/arch/arm/kvm/base_cpu.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2015 ARM Limited
+ * Copyright (c) 2012, 2015, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -88,20 +88,31 @@ BaseArmKvmCPU::startup()
Tick
BaseArmKvmCPU::kvmRun(Tick ticks)
{
- bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
- bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
+ const bool simFIQ(interrupts[0]->checkRaw(INT_FIQ));
+ const bool simIRQ(interrupts[0]->checkRaw(INT_IRQ));
- if (fiqAsserted != simFIQ) {
- fiqAsserted = simFIQ;
- DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
- vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
- }
- if (irqAsserted != simIRQ) {
- irqAsserted = simIRQ;
- DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
- vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
+ if (!vm.hasKernelIRQChip()) {
+ if (fiqAsserted != simFIQ) {
+ DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
+ vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
+ }
+ if (irqAsserted != simIRQ) {
+ DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
+ vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
+ }
+ } else {
+ warn_if(simFIQ && !fiqAsserted,
+ "FIQ raised by the simulated interrupt controller " \
+ "despite in-kernel GIC emulation. This is probably a bug.");
+
+ warn_if(simIRQ && !irqAsserted,
+ "IRQ raised by the simulated interrupt controller " \
+ "despite in-kernel GIC emulation. This is probably a bug.");
}
+ irqAsserted = simIRQ;
+ fiqAsserted = simFIQ;
+
return BaseKvmCPU::kvmRun(ticks);
}