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-rw-r--r--src/arch/arm/miscregs.cc2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index fd861befc..13dec0add 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -451,8 +451,6 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
// Implementation defined
break;
}
- warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n",
- crn, opc1, crm, opc2);
// Unrecognized register
return NUM_MISCREGS;
}