diff options
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 5a1ef5a6a..e14be7fd4 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -488,7 +488,14 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) break; } } else if (opc1 == 4) { - if (crm == 3) { + if (crm == 0) { + switch (opc2) { + case 1: + return MISCREG_TLBIIPAS2IS; + case 5: + return MISCREG_TLBIIPAS2LIS; + } + } else if (crm == 3) { switch (opc2) { case 0: return MISCREG_TLBIALLHIS; @@ -499,6 +506,13 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) case 5: return MISCREG_TLBIMVALHIS; } + } else if (crm == 4) { + switch (opc2) { + case 1: + return MISCREG_TLBIIPAS2; + case 5: + return MISCREG_TLBIIPAS2L; + } } else if (crm == 7) { switch (opc2) { case 0: @@ -2932,10 +2946,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIMVAAL) .writes(1).exceptUserMode(); InitReg(MISCREG_TLBIIPAS2IS) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2LIS) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIALLHIS) .monNonSecureWrite().hypWrite(); @@ -2946,10 +2958,8 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBIMVALHIS) .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIIPAS2L) - .unimplemented() .monNonSecureWrite().hypWrite(); InitReg(MISCREG_TLBIALLH) .monNonSecureWrite().hypWrite(); |