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-rw-r--r--src/arch/arm/miscregs.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index b5ae4ced2..66159132d 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1689,6 +1689,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
switch (op2) {
case 0:
return MISCREG_TTBR0_EL2;
+ case 1:
+ return MISCREG_TTBR1_EL2;
case 2:
return MISCREG_TCR_EL2;
}
@@ -3519,6 +3521,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TTBR0_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTTBR);
+ InitReg(MISCREG_TTBR1_EL2)
+ .unimplemented();
InitReg(MISCREG_TCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTCR);