summaryrefslogtreecommitdiff
path: root/src/arch/arm/miscregs.cc
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/miscregs.cc')
-rw-r--r--src/arch/arm/miscregs.cc3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 08e37bb70..31b3580be 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4007,9 +4007,6 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_CP15_UNIMPL)
.unimplemented()
.warnNotFail();
- InitReg(MISCREG_A64_UNIMPL)
- .unimplemented()
- .warnNotFail();
InitReg(MISCREG_UNKNOWN);
// Register mappings for some unimplemented registers: