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-rw-r--r--src/arch/arm/miscregs.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 729cb4e8b..3a40a27b0 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1334,6 +1334,8 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")),
// MISCREG_CBAR_EL1
bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")),
+ // MISCREG_CONTEXTIDR_EL2
+ bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")),
// Dummy registers
// MISCREG_NOP
@@ -3343,6 +3345,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
switch (crm) {
case 0:
switch (op2) {
+ case 1:
+ return MISCREG_CONTEXTIDR_EL2;
case 2:
return MISCREG_TPIDR_EL2;
}