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-rw-r--r--src/arch/arm/miscregs.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index aedc0fce5..e4375fb8a 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -38,6 +38,7 @@
*/
#include "arch/arm/miscregs.hh"
+#include "base/misc.hh"
namespace ArmISA
{
@@ -424,6 +425,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
// Implementation defined
break;
}
+ warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n",
+ crn, opc1, crm, opc2);
// Unrecognized register
return NUM_MISCREGS;
}