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-rw-r--r--src/arch/arm/miscregs.cc16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index cab5a70d2..bbd5347e5 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2331,6 +2331,16 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
return MISCREG_CNTHP_CVAL_EL2;
}
break;
+ case 3:
+ switch (op2) {
+ case 0:
+ return MISCREG_CNTHV_TVAL_EL2;
+ case 1:
+ return MISCREG_CNTHV_CTL_EL2;
+ case 2:
+ return MISCREG_CNTHV_CVAL_EL2;
+ }
+ break;
}
break;
case 7:
@@ -4018,6 +4028,12 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CONTEXTIDR_EL2)
.mon().hyp();
+ InitReg(MISCREG_CNTHV_CTL_EL2)
+ .mon().hyp();
+ InitReg(MISCREG_CNTHV_CVAL_EL2)
+ .mon().hyp();
+ InitReg(MISCREG_CNTHV_TVAL_EL2)
+ .mon().hyp();
// Dummy registers
InitReg(MISCREG_NOP)