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-rw-r--r--src/arch/arm/miscregs.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 7283b205f..87cc3fde3 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1117,7 +1117,7 @@ canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
- switch (opModeToEL((OperatingMode) (uint8_t) cpsr.mode)) {
+ switch (currEL(cpsr)) {
case EL0:
return secure ? miscRegInfo[reg][MISCREG_USR_S_RD] :
miscRegInfo[reg][MISCREG_USR_NS_RD];
@@ -1140,7 +1140,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
- ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t) cpsr.mode);
+ ExceptionLevel el = currEL(cpsr);
if (reg == MISCREG_DAIF) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uma)