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-rw-r--r--src/arch/arm/miscregs.cc6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index cad123fcc..0bae01893 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1075,6 +1075,12 @@ snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
return reg_as_int;
}
+int
+snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc)
+{
+ SCR scr = tc->readMiscReg(MISCREG_SCR);
+ return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns);
+}
/**
* If the reg is a child reg of a banked set, then the parent is the last