diff options
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 46 |
1 files changed, 45 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 1d4002a03..5fd7d2c53 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1695,7 +1695,11 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_ID_AA64PFR0_EL1; case 1: return MISCREG_ID_AA64PFR1_EL1; - case 2 ... 7: + case 2 ... 3: + return MISCREG_RAZ; + case 4: + return MISCREG_ID_AA64ZFR0_EL1; + case 5 ... 7: return MISCREG_RAZ; } break; @@ -1804,6 +1808,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_CPACR_EL1; } break; + case 2: + switch (op2) { + case 0: + return MISCREG_ZCR_EL1; + } + break; } break; case 4: @@ -1830,6 +1840,22 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_HACR_EL2; } break; + case 2: + switch (op2) { + case 0: + return MISCREG_ZCR_EL2; + } + break; + } + break; + case 5: + switch (crm) { + case 2: + switch (op2) { + case 0: + return MISCREG_ZCR_EL12; + } + break; } break; case 6: @@ -1852,6 +1878,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_CPTR_EL3; } break; + case 2: + switch (op2) { + case 0: + return MISCREG_ZCR_EL3; + } + break; case 3: switch (op2) { case 1: @@ -4923,6 +4955,18 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_CNTHV_TVAL_EL2) .mon().hyp(); + // SVE + InitReg(MISCREG_ID_AA64ZFR0_EL1) + .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ZCR_EL3) + .mon(); + InitReg(MISCREG_ZCR_EL2) + .hyp().mon(); + InitReg(MISCREG_ZCR_EL12) + .unimplemented().warnNotFail(); + InitReg(MISCREG_ZCR_EL1) + .allPrivileges().exceptUserMode(); + // Dummy registers InitReg(MISCREG_NOP) .allPrivileges(); |