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-rw-r--r--src/arch/arm/miscregs.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f87cc3ad5..c506455f8 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -174,9 +174,9 @@ namespace ArmISA
MISCREG_CPSR_MODE,
MISCREG_LOCKFLAG,
MISCREG_LOCKADDR,
+ MISCREG_ID_PFR1,
MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
- MISCREG_ID_PFR1,
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
MISCREG_ID_MMFR1,
@@ -236,10 +236,10 @@ namespace ArmISA
"pmceid1", "pmc_other", "pmxevcntr",
"pmuserenr", "pmintenset", "pmintenclr",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
- "cpsr_mode", "lockflag", "lockaddr",
+ "cpsr_mode", "lockflag", "lockaddr", "id_pfr1",
// Unimplemented below
"tcmtr",
- "id_pfr1", "id_dfr0", "id_afr0",
+ "id_dfr0", "id_afr0",
"id_mmfr1", "id_mmfr2",
"aidr", "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",