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-rw-r--r--src/arch/arm/miscregs.hh10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index cb4dcab8c..9bca3d116 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -677,7 +677,7 @@ namespace ArmISA
// NUM_PHYS_MISCREGS specifies the number of actual physical
// registers, not considering the following pseudo-registers
- // (dummy registers), like UNKNOWN, CP15_UNIMPL...
+ // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
// Checkpointing should use this physical index when
// saving/restoring register values.
NUM_PHYS_MISCREGS = 606, // 606
@@ -690,6 +690,11 @@ namespace ArmISA
MISCREG_A64_UNIMPL,
MISCREG_UNKNOWN,
+ // Implementation defined register: this represent
+ // a pool of unimplemented registers whose access can throw
+ // either UNDEFINED or hypervisor trap exception.
+ MISCREG_IMPDEF_UNIMPL,
+
// Total number of Misc Registers: Physical + Dummy
NUM_MISCREGS
};
@@ -1380,7 +1385,8 @@ namespace ArmISA
"cp14_unimpl",
"cp15_unimpl",
"a64_unimpl",
- "unknown"
+ "unknown",
+ "impl_defined"
};
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,