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Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index c506455f8..813b98b69 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -269,7 +269,10 @@ namespace ArmISA // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. - static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMaskF = 0xF0000000; + static const uint32_t CondCodesMaskQ = 0x08000000; + static const uint32_t CondCodesMaskGE = 0x000F0000; BitUnion32(SCTLR) Bitfield<31> ie; // Instruction endianness |