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-rw-r--r--src/arch/arm/miscregs.hh29
1 files changed, 24 insertions, 5 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 267626e74..86a11d508 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -147,12 +147,27 @@ namespace ArmISA
MISCREG_V2POWPW,
MISCREG_V2POWUR,
MISCREG_V2POWUW,
+ MISCREG_ID_MMFR0,
+ MISCREG_ACTLR,
+ MISCREG_PMCR,
+ MISCREG_PMCCNTR,
+ MISCREG_PMCNTENSET,
+ MISCREG_PMCNTENCLR,
+ MISCREG_PMOVSR,
+ MISCREG_PMSWINC,
+ MISCREG_PMSELR,
+ MISCREG_PMCEID0,
+ MISCREG_PMCEID1,
+ MISCREG_PMC_OTHER,
+ MISCREG_PMXEVCNTR,
+ MISCREG_PMUSERENR,
+ MISCREG_PMINTENSET,
+ MISCREG_PMINTENCLR,
MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR = MISCREG_CP15_UNIMP_START,
MISCREG_ID_PFR1,
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
- MISCREG_ID_MMFR0,
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3,
@@ -163,7 +178,6 @@ namespace ArmISA
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
MISCREG_AIDR,
- MISCREG_ACTLR,
MISCREG_ADFSR,
MISCREG_AIFSR,
MISCREG_DCIMVAC,
@@ -210,12 +224,17 @@ namespace ArmISA
"scr", "sder", "par",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
- // Unimplemented below
+ "id_mmfr0","actlr", "pmcr", "pmcntr",
+ "pmcntenset", "pmcntenclr", "pmovsr",
+ "pmswinc", "pmselr", "pmceid0",
+ "pmceid1", "pmc_other", "pmxevcntr",
+ "pmuserenr", "pmintenset", "pmintenclr",
+ // Unimplemented below
"tcmtr",
"id_pfr1", "id_dfr0", "id_afr0",
- "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
+ "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
- "aidr", "actlr",
+ "aidr",
"adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",