diff options
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 436 |
1 files changed, 436 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index dcaaa7fe3..0d40b27a4 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -673,6 +673,224 @@ namespace ArmISA MISCREG_CNTHV_TVAL_EL2, MISCREG_ID_AA64MMFR2_EL1, + + // GICv3, CPU interface + MISCREG_ICC_PMR_EL1, + MISCREG_ICC_IAR0_EL1, + MISCREG_ICC_EOIR0_EL1, + MISCREG_ICC_HPPIR0_EL1, + MISCREG_ICC_BPR0_EL1, + MISCREG_ICC_AP0R0_EL1, + MISCREG_ICC_AP0R1_EL1, + MISCREG_ICC_AP0R2_EL1, + MISCREG_ICC_AP0R3_EL1, + MISCREG_ICC_AP1R0_EL1, + MISCREG_ICC_AP1R0_EL1_NS, + MISCREG_ICC_AP1R0_EL1_S, + MISCREG_ICC_AP1R1_EL1, + MISCREG_ICC_AP1R1_EL1_NS, + MISCREG_ICC_AP1R1_EL1_S, + MISCREG_ICC_AP1R2_EL1, + MISCREG_ICC_AP1R2_EL1_NS, + MISCREG_ICC_AP1R2_EL1_S, + MISCREG_ICC_AP1R3_EL1, + MISCREG_ICC_AP1R3_EL1_NS, + MISCREG_ICC_AP1R3_EL1_S, + MISCREG_ICC_DIR_EL1, + MISCREG_ICC_RPR_EL1, + MISCREG_ICC_SGI1R_EL1, + MISCREG_ICC_ASGI1R_EL1, + MISCREG_ICC_SGI0R_EL1, + MISCREG_ICC_IAR1_EL1, + MISCREG_ICC_EOIR1_EL1, + MISCREG_ICC_HPPIR1_EL1, + MISCREG_ICC_BPR1_EL1, + MISCREG_ICC_BPR1_EL1_NS, + MISCREG_ICC_BPR1_EL1_S, + MISCREG_ICC_CTLR_EL1, + MISCREG_ICC_CTLR_EL1_NS, + MISCREG_ICC_CTLR_EL1_S, + MISCREG_ICC_SRE_EL1, + MISCREG_ICC_SRE_EL1_NS, + MISCREG_ICC_SRE_EL1_S, + MISCREG_ICC_IGRPEN0_EL1, + MISCREG_ICC_IGRPEN1_EL1, + MISCREG_ICC_IGRPEN1_EL1_NS, + MISCREG_ICC_IGRPEN1_EL1_S, + MISCREG_ICC_SRE_EL2, + MISCREG_ICC_CTLR_EL3, + MISCREG_ICC_SRE_EL3, + MISCREG_ICC_IGRPEN1_EL3, + + // GICv3, CPU interface, virtualization + MISCREG_ICH_AP0R0_EL2, + MISCREG_ICH_AP0R1_EL2, + MISCREG_ICH_AP0R2_EL2, + MISCREG_ICH_AP0R3_EL2, + MISCREG_ICH_AP1R0_EL2, + MISCREG_ICH_AP1R1_EL2, + MISCREG_ICH_AP1R2_EL2, + MISCREG_ICH_AP1R3_EL2, + MISCREG_ICH_HCR_EL2, + MISCREG_ICH_VTR_EL2, + MISCREG_ICH_MISR_EL2, + MISCREG_ICH_EISR_EL2, + MISCREG_ICH_ELRSR_EL2, + MISCREG_ICH_VMCR_EL2, + MISCREG_ICH_LR0_EL2, + MISCREG_ICH_LR1_EL2, + MISCREG_ICH_LR2_EL2, + MISCREG_ICH_LR3_EL2, + MISCREG_ICH_LR4_EL2, + MISCREG_ICH_LR5_EL2, + MISCREG_ICH_LR6_EL2, + MISCREG_ICH_LR7_EL2, + MISCREG_ICH_LR8_EL2, + MISCREG_ICH_LR9_EL2, + MISCREG_ICH_LR10_EL2, + MISCREG_ICH_LR11_EL2, + MISCREG_ICH_LR12_EL2, + MISCREG_ICH_LR13_EL2, + MISCREG_ICH_LR14_EL2, + MISCREG_ICH_LR15_EL2, + + MISCREG_ICV_PMR_EL1, + MISCREG_ICV_IAR0_EL1, + MISCREG_ICV_EOIR0_EL1, + MISCREG_ICV_HPPIR0_EL1, + MISCREG_ICV_BPR0_EL1, + MISCREG_ICV_AP0R0_EL1, + MISCREG_ICV_AP0R1_EL1, + MISCREG_ICV_AP0R2_EL1, + MISCREG_ICV_AP0R3_EL1, + MISCREG_ICV_AP1R0_EL1, + MISCREG_ICV_AP1R0_EL1_NS, + MISCREG_ICV_AP1R0_EL1_S, + MISCREG_ICV_AP1R1_EL1, + MISCREG_ICV_AP1R1_EL1_NS, + MISCREG_ICV_AP1R1_EL1_S, + MISCREG_ICV_AP1R2_EL1, + MISCREG_ICV_AP1R2_EL1_NS, + MISCREG_ICV_AP1R2_EL1_S, + MISCREG_ICV_AP1R3_EL1, + MISCREG_ICV_AP1R3_EL1_NS, + MISCREG_ICV_AP1R3_EL1_S, + MISCREG_ICV_DIR_EL1, + MISCREG_ICV_RPR_EL1, + MISCREG_ICV_SGI1R_EL1, + MISCREG_ICV_ASGI1R_EL1, + MISCREG_ICV_SGI0R_EL1, + MISCREG_ICV_IAR1_EL1, + MISCREG_ICV_EOIR1_EL1, + MISCREG_ICV_HPPIR1_EL1, + MISCREG_ICV_BPR1_EL1, + MISCREG_ICV_BPR1_EL1_NS, + MISCREG_ICV_BPR1_EL1_S, + MISCREG_ICV_CTLR_EL1, + MISCREG_ICV_CTLR_EL1_NS, + MISCREG_ICV_CTLR_EL1_S, + MISCREG_ICV_SRE_EL1, + MISCREG_ICV_SRE_EL1_NS, + MISCREG_ICV_SRE_EL1_S, + MISCREG_ICV_IGRPEN0_EL1, + MISCREG_ICV_IGRPEN1_EL1, + MISCREG_ICV_IGRPEN1_EL1_NS, + MISCREG_ICV_IGRPEN1_EL1_S, + + MISCREG_ICC_AP0R0, + MISCREG_ICC_AP0R1, + MISCREG_ICC_AP0R2, + MISCREG_ICC_AP0R3, + MISCREG_ICC_AP1R0, + MISCREG_ICC_AP1R0_NS, + MISCREG_ICC_AP1R0_S, + MISCREG_ICC_AP1R1, + MISCREG_ICC_AP1R1_NS, + MISCREG_ICC_AP1R1_S, + MISCREG_ICC_AP1R2, + MISCREG_ICC_AP1R2_NS, + MISCREG_ICC_AP1R2_S, + MISCREG_ICC_AP1R3, + MISCREG_ICC_AP1R3_NS, + MISCREG_ICC_AP1R3_S, + MISCREG_ICC_ASGI1R, + MISCREG_ICC_BPR0, + MISCREG_ICC_BPR1, + MISCREG_ICC_BPR1_NS, + MISCREG_ICC_BPR1_S, + MISCREG_ICC_CTLR, + MISCREG_ICC_CTLR_NS, + MISCREG_ICC_CTLR_S, + MISCREG_ICC_DIR, + MISCREG_ICC_EOIR0, + MISCREG_ICC_EOIR1, + MISCREG_ICC_HPPIR0, + MISCREG_ICC_HPPIR1, + MISCREG_ICC_HSRE, + MISCREG_ICC_IAR0, + MISCREG_ICC_IAR1, + MISCREG_ICC_IGRPEN0, + MISCREG_ICC_IGRPEN1, + MISCREG_ICC_IGRPEN1_NS, + MISCREG_ICC_IGRPEN1_S, + MISCREG_ICC_MCTLR, + MISCREG_ICC_MGRPEN1, + MISCREG_ICC_MSRE, + MISCREG_ICC_PMR, + MISCREG_ICC_RPR, + MISCREG_ICC_SGI0R, + MISCREG_ICC_SGI1R, + MISCREG_ICC_SRE, + MISCREG_ICC_SRE_NS, + MISCREG_ICC_SRE_S, + + MISCREG_ICH_AP0R0, + MISCREG_ICH_AP0R1, + MISCREG_ICH_AP0R2, + MISCREG_ICH_AP0R3, + MISCREG_ICH_AP1R0, + MISCREG_ICH_AP1R1, + MISCREG_ICH_AP1R2, + MISCREG_ICH_AP1R3, + MISCREG_ICH_HCR, + MISCREG_ICH_VTR, + MISCREG_ICH_MISR, + MISCREG_ICH_EISR, + MISCREG_ICH_ELRSR, + MISCREG_ICH_VMCR, + MISCREG_ICH_LR0, + MISCREG_ICH_LR1, + MISCREG_ICH_LR2, + MISCREG_ICH_LR3, + MISCREG_ICH_LR4, + MISCREG_ICH_LR5, + MISCREG_ICH_LR6, + MISCREG_ICH_LR7, + MISCREG_ICH_LR8, + MISCREG_ICH_LR9, + MISCREG_ICH_LR10, + MISCREG_ICH_LR11, + MISCREG_ICH_LR12, + MISCREG_ICH_LR13, + MISCREG_ICH_LR14, + MISCREG_ICH_LR15, + MISCREG_ICH_LRC0, + MISCREG_ICH_LRC1, + MISCREG_ICH_LRC2, + MISCREG_ICH_LRC3, + MISCREG_ICH_LRC4, + MISCREG_ICH_LRC5, + MISCREG_ICH_LRC6, + MISCREG_ICH_LRC7, + MISCREG_ICH_LRC8, + MISCREG_ICH_LRC9, + MISCREG_ICH_LRC10, + MISCREG_ICH_LRC11, + MISCREG_ICH_LRC12, + MISCREG_ICH_LRC13, + MISCREG_ICH_LRC14, + MISCREG_ICH_LRC15, + // These MISCREG_FREESLOT are available Misc Register // slots for future registers to be implemented. MISCREG_FREESLOT_1, @@ -1389,6 +1607,224 @@ namespace ArmISA "cnthv_cval_el2", "cnthv_tval_el2", "id_aa64mmfr2_el1", + + // GICv3, CPU interface + "icc_pmr_el1", + "icc_iar0_el1", + "icc_eoir0_el1", + "icc_hppir0_el1", + "icc_bpr0_el1", + "icc_ap0r0_el1", + "icc_ap0r1_el1", + "icc_ap0r2_el1", + "icc_ap0r3_el1", + "icc_ap1r0_el1", + "icc_ap1r0_el1_ns", + "icc_ap1r0_el1_s", + "icc_ap1r1_el1", + "icc_ap1r1_el1_ns", + "icc_ap1r1_el1_s", + "icc_ap1r2_el1", + "icc_ap1r2_el1_ns", + "icc_ap1r2_el1_s", + "icc_ap1r3_el1", + "icc_ap1r3_el1_ns", + "icc_ap1r3_el1_s", + "icc_dir_el1", + "icc_rpr_el1", + "icc_sgi1r_el1", + "icc_asgi1r_el1", + "icc_sgi0r_el1", + "icc_iar1_el1", + "icc_eoir1_el1", + "icc_hppir1_el1", + "icc_bpr1_el1", + "icc_bpr1_el1_ns", + "icc_bpr1_el1_s", + "icc_ctlr_el1", + "icc_ctlr_el1_ns", + "icc_ctlr_el1_s", + "icc_sre_el1", + "icc_sre_el1_ns", + "icc_sre_el1_s", + "icc_igrpen0_el1", + "icc_igrpen1_el1", + "icc_igrpen1_el1_ns", + "icc_igrpen1_el1_s", + "icc_sre_el2", + "icc_ctlr_el3", + "icc_sre_el3", + "icc_igrpen1_el3", + + // GICv3, CPU interface, virtualization + "ich_ap0r0_el2", + "ich_ap0r1_el2", + "ich_ap0r2_el2", + "ich_ap0r3_el2", + "ich_ap1r0_el2", + "ich_ap1r1_el2", + "ich_ap1r2_el2", + "ich_ap1r3_el2", + "ich_hcr_el2", + "ich_vtr_el2", + "ich_misr_el2", + "ich_eisr_el2", + "ich_elrsr_el2", + "ich_vmcr_el2", + "ich_lr0_el2", + "ich_lr1_el2", + "ich_lr2_el2", + "ich_lr3_el2", + "ich_lr4_el2", + "ich_lr5_el2", + "ich_lr6_el2", + "ich_lr7_el2", + "ich_lr8_el2", + "ich_lr9_el2", + "ich_lr10_el2", + "ich_lr11_el2", + "ich_lr12_el2", + "ich_lr13_el2", + "ich_lr14_el2", + "ich_lr15_el2", + + "icv_pmr_el1", + "icv_iar0_el1", + "icv_eoir0_el1", + "icv_hppir0_el1", + "icv_bpr0_el1", + "icv_ap0r0_el1", + "icv_ap0r1_el1", + "icv_ap0r2_el1", + "icv_ap0r3_el1", + "icv_ap1r0_el1", + "icv_ap1r0_el1_ns", + "icv_ap1r0_el1_s", + "icv_ap1r1_el1", + "icv_ap1r1_el1_ns", + "icv_ap1r1_el1_s", + "icv_ap1r2_el1", + "icv_ap1r2_el1_ns", + "icv_ap1r2_el1_s", + "icv_ap1r3_el1", + "icv_ap1r3_el1_ns", + "icv_ap1r3_el1_s", + "icv_dir_el1", + "icv_rpr_el1", + "icv_sgi1r_el1", + "icv_asgi1r_el1", + "icv_sgi0r_el1", + "icv_iar1_el1", + "icv_eoir1_el1", + "icv_hppir1_el1", + "icv_bpr1_el1", + "icv_bpr1_el1_ns", + "icv_bpr1_el1_s", + "icv_ctlr_el1", + "icv_ctlr_el1_ns", + "icv_ctlr_el1_s", + "icv_sre_el1", + "icv_sre_el1_ns", + "icv_sre_el1_s", + "icv_igrpen0_el1", + "icv_igrpen1_el1", + "icv_igrpen1_el1_ns", + "icv_igrpen1_el1_s", + + "icc_ap0r0", + "icc_ap0r1", + "icc_ap0r2", + "icc_ap0r3", + "icc_ap1r0", + "icc_ap1r0_ns", + "icc_ap1r0_s", + "icc_ap1r1", + "icc_ap1r1_ns", + "icc_ap1r1_s", + "icc_ap1r2", + "icc_ap1r2_ns", + "icc_ap1r2_s", + "icc_ap1r3", + "icc_ap1r3_ns", + "icc_ap1r3_s", + "icc_asgi1r", + "icc_bpr0", + "icc_bpr1", + "icc_bpr1_ns", + "icc_bpr1_s", + "icc_ctlr", + "icc_ctlr_ns", + "icc_ctlr_s", + "icc_dir", + "icc_eoir0", + "icc_eoir1", + "icc_hppir0", + "icc_hppir1", + "icc_hsre", + "icc_iar0", + "icc_iar1", + "icc_igrpen0", + "icc_igrpen1", + "icc_igrpen1_ns", + "icc_igrpen1_s", + "icc_mctlr", + "icc_mgrpen1", + "icc_msre", + "icc_pmr", + "icc_rpr", + "icc_sgi0r", + "icc_sgi1r", + "icc_sre", + "icc_sre_ns", + "icc_sre_s", + + "ich_ap0r0", + "ich_ap0r1", + "ich_ap0r2", + "ich_ap0r3", + "ich_ap1r0", + "ich_ap1r1", + "ich_ap1r2", + "ich_ap1r3", + "ich_hcr", + "ich_vtr", + "ich_misr", + "ich_eisr", + "ich_elrsr", + "ich_vmcr", + "ich_lr0", + "ich_lr1", + "ich_lr2", + "ich_lr3", + "ich_lr4", + "ich_lr5", + "ich_lr6", + "ich_lr7", + "ich_lr8", + "ich_lr9", + "ich_lr10", + "ich_lr11", + "ich_lr12", + "ich_lr13", + "ich_lr14", + "ich_lr15", + "ich_lrc0", + "ich_lrc1", + "ich_lrc2", + "ich_lrc3", + "ich_lrc4", + "ich_lrc5", + "ich_lrc6", + "ich_lrc7", + "ich_lrc8", + "ich_lrc9", + "ich_lrc10", + "ich_lrc11", + "ich_lrc12", + "ich_lrc13", + "ich_lrc14", + "ich_lrc15", + "freeslot2", "num_phys_regs", |