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-rw-r--r--src/arch/arm/miscregs_types.hh1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index 0a862360e..c3ee6ca00 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -319,7 +319,6 @@ namespace ArmISA
// DC CVAC and IC IVAU instructions
// (AArch64 SCTLR_EL1 only)
Bitfield<25> ee; // Exception Endianness
- Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
// (AArch64 SCTLR_EL1 only)
Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)