diff options
Diffstat (limited to 'src/arch/arm/regfile')
| -rw-r--r-- | src/arch/arm/regfile/float_regfile.hh | 181 | ||||
| -rw-r--r-- | src/arch/arm/regfile/int_regfile.hh | 114 | ||||
| -rw-r--r-- | src/arch/arm/regfile/misc_regfile.hh | 100 | ||||
| -rw-r--r-- | src/arch/arm/regfile/regfile.cc | 86 | ||||
| -rw-r--r-- | src/arch/arm/regfile/regfile.hh | 203 |
5 files changed, 684 insertions, 0 deletions
diff --git a/src/arch/arm/regfile/float_regfile.hh b/src/arch/arm/regfile/float_regfile.hh new file mode 100644 index 000000000..757f5f0df --- /dev/null +++ b/src/arch/arm/regfile/float_regfile.hh @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Stephen Hines + */ + +#ifndef __ARCH_ARM_REGFILE_FLOAT_REGFILE_HH__ +#define __ARCH_ARM_REGFILE_FLOAT_REGFILE_HH__ + +#include "arch/arm/types.hh" +#include "arch/arm/isa_traits.hh" +#include "base/misc.hh" +#include "base/bitfield.hh" +#include "sim/faults.hh" +#include "sim/serialize.hh" + +#include <string> + +class Checkpoint; + +namespace ArmISA +{ + static inline std::string getFloatRegName(RegIndex) + { + return ""; + } + + const uint32_t ARM32_QNAN = 0x7fbfffff; + const uint64_t ARM64_QNAN = ULL(0x7fbfffffffffffff); + + enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR + }; + + enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented + }; + + enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 + }; + + const int SingleWidth = 32; + const int SingleBytes = SingleWidth / 4; + + const int DoubleWidth = 64; + const int DoubleBytes = DoubleWidth / 4; + + const int QuadWidth = 128; + const int QuadBytes = QuadWidth / 4; + + class FloatRegFile + { + protected: + union { + FloatRegBits qregs[NumFloatRegs]; + FloatRegVal regs[NumFloatRegs]; + }; + + public: + + void clear() + { + bzero(regs, sizeof(regs)); + regs[8] = 0.0; + regs[9] = 1.0; + regs[10] = 2.0; + regs[11] = 3.0; + regs[12] = 4.0; + regs[13] = 5.0; + regs[14] = 0.5; + regs[15] = 10.0; + } + + FloatRegVal readReg(int floatReg, int width) + { + return regs[floatReg]; + } + + FloatRegBits readRegBits(int floatReg, int width) + { + //return qregs[floatReg]; + switch(width) + { + case SingleWidth: + { + union { + float f; + uint32_t i; + } s; + s.f = (float) regs[floatReg]; + return s.i; + } + case DoubleWidth: + { + uint64_t tmp = (qregs[floatReg]<<32|qregs[floatReg]>>32); + return tmp; + } + default: + panic("Attempted to read a %d bit floating point " + "register!", width); + + } + } + + Fault setReg(int floatReg, const FloatRegVal &val, int width) + { + if (floatReg > 7) + panic("Writing to a hard-wired FP register"); + regs[floatReg] = val; + return NoFault; + } + + Fault setRegBits(int floatReg, const FloatRegBits &val, int width) + { + if (floatReg > 7) + panic("Writing to a hard-wired FP register"); + switch(width) + { + case DoubleWidth: + { + uint64_t tmp = (val << 32 | val >> 32); + qregs[floatReg] = tmp; + return NoFault; + } + case SingleWidth: + default: + panic("Attempted to write a %d bit floating point " + "register!", width); + } + } + + void serialize(std::ostream &os) + { + SERIALIZE_ARRAY(regs, NumFloatRegs); + } + + void unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(regs, NumFloatRegs); + } + }; + +} // namespace ArmISA + +#endif diff --git a/src/arch/arm/regfile/int_regfile.hh b/src/arch/arm/regfile/int_regfile.hh new file mode 100644 index 000000000..938e68816 --- /dev/null +++ b/src/arch/arm/regfile/int_regfile.hh @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Stephen Hines + */ + +#ifndef __ARCH_ARM_REGFILE_INT_REGFILE_HH__ +#define __ARCH_ARM_REGFILE_INT_REGFILE_HH__ + +#include "arch/arm/isa_traits.hh" +#include "arch/arm/types.hh" +#include "base/misc.hh" +#include "sim/faults.hh" +#include "sim/serialize.hh" + +class Checkpoint; +class ThreadContext; + +namespace ArmISA +{ + static inline std::string getIntRegName(RegIndex) + { + return ""; + } + + enum MiscIntRegNums { + zero_reg = NumIntArchRegs, + addr_reg, + + rhi, + rlo, + + r8_fiq, /* FIQ mode register bank */ + r9_fiq, + r10_fiq, + r11_fiq, + r12_fiq, + + r13_fiq, /* FIQ mode SP and LR */ + r14_fiq, + + r13_irq, /* IRQ mode SP and LR */ + r14_irq, + + r13_svc, /* SVC mode SP and LR */ + r14_svc, + + r13_undef, /* UNDEF mode SP and LR */ + r14_undef, + + r13_abt, /* ABT mode SP and LR */ + r14_abt + }; + + class IntRegFile + { + protected: + IntReg regs[NumIntRegs]; + + public: + IntReg readReg(int intReg) + { + return regs[intReg]; + } + + void clear() + { + bzero(regs, sizeof(regs)); + } + + Fault setReg(int intReg, const IntReg &val) + { + regs[intReg] = val; + return NoFault; + } + + void serialize(std::ostream &os) + { + SERIALIZE_ARRAY(regs, NumIntRegs); + } + + void unserialize(Checkpoint *cp, const std::string §ion) + { + UNSERIALIZE_ARRAY(regs, NumIntRegs); + } + }; + +} // namespace ArmISA + +#endif diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh new file mode 100644 index 000000000..f8301bed2 --- /dev/null +++ b/src/arch/arm/regfile/misc_regfile.hh @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Stephen Hines + */ + +#ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__ +#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__ + +#include "arch/arm/types.hh" +#include "sim/faults.hh" + +class ThreadContext; + +namespace ArmISA +{ + static inline std::string getMiscRegName(RegIndex) + { + return ""; + } + + //Coprocessor 0 Register Names + enum MiscRegTags { + // Status Registers for the ARM + // + // CPSR Layout + // 31302928 ... 7 6 5 4 3 2 1 0 + // N Z C V ... I F T { MODE } + CPSR = 0, + SPSR_FIQ, + SPSR_IRQ, + SPSR_SVC, + SPSR_UND, + SPSR_ABT, + FPSR + }; + + class MiscRegFile { + + protected: + MiscReg miscRegFile[NumMiscRegs]; + + public: + void clear() + { + // Unknown startup state in misc register file currently + } + + void copyMiscRegs(ThreadContext *tc); + + MiscReg readRegNoEffect(int misc_reg) + { + return miscRegFile[misc_reg]; + } + + MiscReg readReg(int misc_reg, ThreadContext *tc) + { + return miscRegFile[misc_reg]; + } + + void setRegNoEffect(int misc_reg, const MiscReg &val) + { + miscRegFile[misc_reg] = val; + } + + void setReg(int misc_reg, const MiscReg &val, + ThreadContext *tc) + { + miscRegFile[misc_reg] = val; + } + + friend class RegFile; + }; +} // namespace ArmISA + +#endif diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc new file mode 100644 index 000000000..5de0b3076 --- /dev/null +++ b/src/arch/arm/regfile/regfile.cc @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Stephen Hines + */ + +#include "arch/arm/regfile/regfile.hh" +#include "sim/serialize.hh" + +using namespace std; + +namespace ArmISA +{ + +void +copyRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("Copy Regs Not Implemented Yet\n"); +} + +void +copyMiscRegs(ThreadContext *src, ThreadContext *dest) +{ + panic("Copy Misc. Regs Not Implemented Yet\n"); +} + +void +MiscRegFile::copyMiscRegs(ThreadContext *tc) +{ + panic("Copy Misc. Regs Not Implemented Yet\n"); +} + +void +RegFile::serialize(std::ostream &os) +{ + intRegFile.serialize(os); + //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); + //SERIALZE_ARRAY(miscRegFile); + //SERIALIZE_SCALAR(miscRegs.fpcr); + //SERIALIZE_SCALAR(miscRegs.lock_flag); + //SERIALIZE_SCALAR(miscRegs.lock_addr); + //SERIALIZE_SCALAR(pc); + SERIALIZE_SCALAR(npc); + SERIALIZE_SCALAR(nnpc); +} + +void +RegFile::unserialize(Checkpoint *cp, const std::string §ion) +{ + intRegFile.unserialize(cp, section); + //UNSERIALIZE_ARRAY(floatRegFile); + //UNSERIALZE_ARRAY(miscRegFile); + //UNSERIALIZE_SCALAR(miscRegs.fpcr); + //UNSERIALIZE_SCALAR(miscRegs.lock_flag); + //UNSERIALIZE_SCALAR(miscRegs.lock_addr); + //UNSERIALIZE_SCALAR(pc); + UNSERIALIZE_SCALAR(npc); + UNSERIALIZE_SCALAR(nnpc); + +} + +} // namespace ArmISA diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh new file mode 100644 index 000000000..86799f18d --- /dev/null +++ b/src/arch/arm/regfile/regfile.hh @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Stephen Hines + */ + +#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__ +#define __ARCH_ARM_REGFILE_REGFILE_HH__ + +#include "arch/arm/types.hh" +#include "arch/arm/regfile/int_regfile.hh" +#include "arch/arm/regfile/float_regfile.hh" +#include "arch/arm/regfile/misc_regfile.hh" +#include "sim/faults.hh" + +class Checkpoint; +class ThreadContext; + +namespace ArmISA +{ + class RegFile { + protected: + IntRegFile intRegFile; // (signed) integer register file + FloatRegFile floatRegFile; // floating point register file + MiscRegFile miscRegFile; // control register file + + public: + + void clear() + { + intRegFile.clear(); + floatRegFile.clear(); + miscRegFile.clear(); + } + + MiscReg readMiscRegNoEffect(int miscReg) + { + return miscRegFile.readRegNoEffect(miscReg); + } + + MiscReg readMiscReg(int miscReg, ThreadContext *tc) + { + return miscRegFile.readReg(miscReg, tc); + } + + void setMiscRegNoEffect(int miscReg, const MiscReg &val) + { + miscRegFile.setRegNoEffect(miscReg, val); + } + + void setMiscReg(int miscReg, const MiscReg &val, + ThreadContext * tc) + { + miscRegFile.setReg(miscReg, val, tc); + } + + FloatRegVal readFloatReg(int floatReg) + { + return floatRegFile.readReg(floatReg,SingleWidth); + } + + FloatRegVal readFloatReg(int floatReg, int width) + { + return floatRegFile.readReg(floatReg,width); + } + + FloatRegBits readFloatRegBits(int floatReg) + { + return floatRegFile.readRegBits(floatReg,SingleWidth); + } + + FloatRegBits readFloatRegBits(int floatReg, int width) + { + return floatRegFile.readRegBits(floatReg,width); + } + + void setFloatReg(int floatReg, const FloatRegVal &val) + { + floatRegFile.setReg(floatReg, val, SingleWidth); + } + + void setFloatReg(int floatReg, const FloatRegVal &val, int width) + { + floatRegFile.setReg(floatReg, val, width); + } + + void setFloatRegBits(int floatReg, const FloatRegBits &val) + { + floatRegFile.setRegBits(floatReg, val, SingleWidth); + } + + void setFloatRegBits(int floatReg, const FloatRegBits &val, int width) + { + floatRegFile.setRegBits(floatReg, val, width); + } + + IntReg readIntReg(int intReg) + { + // In the Arm, reading from the PC for a generic instruction yields + // the current PC + 8, due to previous pipeline implementations + if (intReg == PCReg) + return intRegFile.readReg(intReg) + 8; + //return pc + 8; + else + return intRegFile.readReg(intReg); + } + + void setIntReg(int intReg, const IntReg &val) + { + // Have to trap writes to PC so that they update NPC instead + if (intReg == PCReg) + setNextPC(val); + else + intRegFile.setReg(intReg, val); + } + protected: + + Addr pc; // program counter + Addr npc; // next-cycle program counter + Addr nnpc; // next-next-cycle program counter + + public: + Addr readPC() + { + return intRegFile.readReg(PCReg); + //return pc; + } + + void setPC(Addr val) + { + intRegFile.setReg(PCReg, val); + //pc = val; + } + + Addr readNextPC() + { + return npc; + } + + void setNextPC(Addr val) + { + npc = val; + } + + Addr readNextNPC() + { + return npc + sizeof(MachInst); + } + + void setNextNPC(Addr val) + { + //nnpc = val; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + + void changeContext(RegContextParam param, RegContextVal val) + { + } + }; + + static inline int flattenIntIndex(ThreadContext * tc, int reg) + { + return reg; + } + + static inline int flattenFloatIndex(ThreadContext * tc, int reg) + { + return reg; + } + + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + +} // namespace ArmISA + +#endif |