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Diffstat (limited to 'src/arch/arm/stage2_mmu.cc')
| -rw-r--r-- | src/arch/arm/stage2_mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index 5c28d073e..ba820e339 100644 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -51,7 +51,7 @@ using namespace ArmISA; Stage2MMU::Stage2MMU(const Params *p) : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), port(_stage1Tlb->getTableWalker(), p->sys), - masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) + masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker())) { // we use the stage-one table walker as the parent of the port, // and to get our master id, this is done to keep things |