1 files changed, 8 insertions, 7 deletions

diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index ba820e339..c6f3ba7c1 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -67,17 +67,17 @@ Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
     Fault fault;
 
     // translate to physical address using the second stage MMU
-    Request req = Request();
-    req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
+    auto req = std::make_shared<Request>();
+    req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
     if (isFunctional) {
-        fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read);
+        fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
     } else {
-        fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read);
+        fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read);
     }
 
     // Now do the access.
-    if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) {
-        Packet pkt = Packet(&req, MemCmd::ReadReq);
+    if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
+        Packet pkt = Packet(req, MemCmd::ReadReq);
         pkt.dataStatic(data);
         if (isFunctional) {
             port.sendFunctional(&pkt);
@@ -116,7 +116,8 @@ Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
 }
 
 void
-Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
+Stage2MMU::Stage2Translation::finish(const Fault &_fault,
+                                     const RequestPtr &req,
                                      ThreadContext *tc, BaseTLB::Mode mode)
 {
     fault = _fault;