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-rwxr-xr-xsrc/arch/arm/stage2_mmu.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh
index d1812c4ed..37eca4f56 100755
--- a/src/arch/arm/stage2_mmu.hh
+++ b/src/arch/arm/stage2_mmu.hh
@@ -78,7 +78,7 @@ class Stage2MMU : public SimObject
markDelayed() {}
void
- finish(Fault fault, RequestPtr req, ThreadContext *tc,
+ finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
BaseTLB::Mode mode);
void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)