diff options
Diffstat (limited to 'src/arch/arm/stage2_mmu.hh')
-rwxr-xr-x | src/arch/arm/stage2_mmu.hh | 58 |
1 files changed, 53 insertions, 5 deletions
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh index 37eca4f56..41a10e623 100755 --- a/src/arch/arm/stage2_mmu.hh +++ b/src/arch/arm/stage2_mmu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013 ARM Limited + * Copyright (c) 2012-2013, 2015 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -55,6 +55,46 @@ class Stage2MMU : public SimObject /** The TLB that will cache the stage 2 look ups. */ TLB *_stage2Tlb; + protected: + + /** + * A snooping DMA port that currently does nothing besides + * extending the DMA port to accept snoops without + * complaining. Currently we take no action on any snoops. + */ + class SnoopingDmaPort : public DmaPort + { + + protected: + + virtual void recvTimingSnoopReq(PacketPtr pkt) + { } + + virtual Tick recvAtomicSnoop(PacketPtr pkt) + { return 0; } + + virtual void recvFunctionalSnoop(PacketPtr pkt) + { } + + virtual bool isSnooping() const { return true; } + + public: + + /** + * A snooping DMA port merely calls the construtor of the DMA + * port. + */ + SnoopingDmaPort(MemObject *dev, System *s) : + DmaPort(dev, s) + { } + }; + + /** Port to issue translation requests from */ + SnoopingDmaPort port; + + /** Request id for requests generated by this MMU */ + MasterID masterId; + public: /** This translation class is used to trigger the data fetch once a timing translation returns the translated physical address */ @@ -96,12 +136,20 @@ class Stage2MMU : public SimObject typedef ArmStage2MMUParams Params; Stage2MMU(const Params *p); + /** + * Get the port that ultimately belongs to the stage-two MMU, but + * is used by the two table walkers, and is exposed externally and + * connected through the stage-one table walker. + */ + DmaPort& getPort() { return port; } + + unsigned int drain(DrainManager *dm); + Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, - uint8_t *data, int numBytes, Request::Flags flags, int masterId, - bool isFunctional); + uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional); Fault readDataTimed(ThreadContext *tc, Addr descAddr, - Stage2Translation *translation, int numBytes, Request::Flags flags, - int masterId); + Stage2Translation *translation, int numBytes, + Request::Flags flags); TLB* stage1Tlb() const { return _stage1Tlb; } TLB* stage2Tlb() const { return _stage2Tlb; } |