1 files changed, 12 insertions, 51 deletions

diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index b265f5165..d9245d595 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2014 ARM Limited
+ * Copyright (c) 2010-2015 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,7 +47,6 @@
 #include "arch/arm/system.hh"
 #include "arch/arm/tlb.hh"
 #include "dev/dma_device.hh"
-#include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/ArmTableWalker.hh"
 #include "sim/eventq.hh"
@@ -812,37 +811,6 @@ class TableWalker : public MemObject
 
   protected:
 
-    /**
-     * A snooping DMA port that currently does nothing besides
-     * extending the DMA port to accept snoops without complaining.
-     */
-    class SnoopingDmaPort : public DmaPort
-    {
-
-      protected:
-
-        virtual void recvTimingSnoopReq(PacketPtr pkt)
-        { }
-
-        virtual Tick recvAtomicSnoop(PacketPtr pkt)
-        { return 0; }
-
-        virtual void recvFunctionalSnoop(PacketPtr pkt)
-        { }
-
-        virtual bool isSnooping() const { return true; }
-
-      public:
-
-        /**
-         * A snooping DMA port merely calls the construtor of the DMA
-         * port.
-         */
-        SnoopingDmaPort(MemObject *dev, System *s) :
-            DmaPort(dev, s)
-        { }
-    };
-
     /** Queues of requests for all the different lookup levels */
     std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
 
@@ -850,16 +818,18 @@ class TableWalker : public MemObject
      * currently busy. */
     std::list<WalkerState *> pendingQueue;
 
-
-    /** Port to issue translation requests from */
-    SnoopingDmaPort port;
-
     /** If we're draining keep the drain event around until we're drained */
     DrainManager *drainManager;
 
     /** The MMU to forward second stage look upts to */
     Stage2MMU *stage2Mmu;
 
+    /** Port shared by the two table walkers. */
+    DmaPort* port;
+
+    /** Master id assigned by the MMU. */
+    MasterID masterId;
+
     /** Indicates whether this table walker is part of the stage 2 mmu */
     const bool isStage2;
 
@@ -874,9 +844,6 @@ class TableWalker : public MemObject
     /** If a timing translation is currently in progress */
     bool pending;
 
-    /** Request id for requests generated by this walker */
-    MasterID masterId;
-
     /** The number of walks belonging to squashed instructions that can be
      * removed from the pendingQueue per cycle. */
     unsigned numSquashable;
@@ -887,7 +854,6 @@ class TableWalker : public MemObject
     bool _haveVirtualization;
     uint8_t physAddrRange;
     bool _haveLargeAsid64;
-    ArmSystem *armSys;
 
     /** Statistics */
     Stats::Scalar statWalks;
@@ -920,6 +886,8 @@ class TableWalker : public MemObject
         return dynamic_cast<const Params *>(_params);
     }
 
+    virtual void init();
+
     bool haveLPAE() const { return _haveLPAE; }
     bool haveVirtualization() const { return _haveVirtualization; }
     bool haveLargeAsid64() const { return _haveLargeAsid64; }
@@ -927,18 +895,11 @@ class TableWalker : public MemObject
     void completeDrain();
     unsigned int drain(DrainManager *dm);
     virtual void drainResume();
+
     virtual BaseMasterPort& getMasterPort(const std::string &if_name,
                                           PortID idx = InvalidPortID);
-    void regStats();
 
-    /**
-     * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
-     * access the table walker port through the TLB so that it can
-     * orchestrate staged translations.
-     *
-     * @return Our DMA port
-     */
-    DmaPort& getWalkerPort() { return port; }
+    void regStats();
 
     Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
                bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
@@ -947,7 +908,7 @@ class TableWalker : public MemObject
 
     void setTlb(TLB *_tlb) { tlb = _tlb; }
     TLB* getTlb() { return tlb; }
-    void setMMU(Stage2MMU *m) { stage2Mmu = m; }
+    void setMMU(Stage2MMU *m, MasterID master_id);
     void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
                   uint8_t texcb, bool s);
     void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,